reg [16:0] pixelcnt;
reg [4:0] hscnt;
reg [11:0] hscount;
reg [2:0] hscnttemp;
reg vga640;
wire hs_temp;
assign hs_temp=hs;
always@(posedge tile1_txusrclk20_i)
begin
hscnttemp[0] <= hs_temp;
hscnttemp[1] <= hscnttemp[0];
hscnttemp[2] <= hscnttemp[1];
end
always@(posedge tile1_txusrclk20_i)
begin
if(hscnttemp[2:1]==2'b10)
hscnt <= hscnt+1;
else if(hscnt==5'b10000)
hscnt <= 5'b00000;
end
always@(posedge tile1_txusrclk20_i)
begin
if(hscnt<5'b10000)
pixelcnt <= pixelcnt+1;
else begin
if(hscnt==5'b10000) begin
if(pixelcnt[16]==1) begin
hscount <= pixelcnt[16:5];
vga640 <= 1'b1;
pixelcnt <= {17{1'b0}};
end
else begin
hscount <= pixelcnt[15:4]-1;
vga640 <= 1'b0;
pixelcnt <= {(17){1'b0}};
end
end
else pixelcnt <= {(17){1'b0}};
end
end
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小平头技术问答
楼主不解啥?
这段代码不知什么意思,具体实现什么?看样子好像不是FPGA内部产生的吧?
初入江湖,恳求赐教……
不知何解??
根据具体应用背景来判断!
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