本人所使用开发板，altera DE2-115    时钟50MHz  （周期20ns）
所设计程序实现流水灯，和数码管显示
由于系统时钟频率很高，所以设计26位计数器进行分频，当计数满时，流水灯流水一次（状态变化一次），因此每当状态变化一次（即计数器计满数）需要2^26个时钟周期，约1秒，但是本人在用modelsim进行仿真时，等了半天，也没仿真到1秒的时刻，请问各位大侠有什么办法吗？
小弟把程序给大家附上来，希望高手指点一下
//源程序：
module led_flow(sys_clk,rst_n,led,seg);
input sys_clk,rst_n; //50MHz input clock
output [17:0] led; //led number : 3
output [6:0] seg; //seg led
reg [25:0] count; //the clock is high,count : fenpin
reg [17:0] led; //when low level,led flash
reg [6:0] seg;//seg led
reg [4:0] flag;
always @(posedge sys_clk,negedge rst_n)
if(!rst_n)
  begin
  flag <= 5'b0;
  count <= 26'b0;
  end
else
  begin
  if( count == 26'b11_1111_1111_1111_1111_1111_1110 )
    begin
    count <= 26'b0;
    if(flag == 5'b1_0001)
      flag <= 5'b0_0000;
    else
      flag <= flag+2'b01;
    end
  else
    count <= count + 1;
  end
always @(posedge sys_clk)
begin
  case(flag)
  5'b0_0000:
  begin
    led <= 18'b00_0000_0000_0000_0001;
    seg <= 7'b1000000;//0
  end
  5'b0_0001:
  begin
    led <= 18'b00_0000_0000_0000_0010;
    seg <= 7'b1111001;//1
  end
  5'b0_0010:
  begin
    led <= 18'b00_0000_0000_0000_0100;
    seg <= 7'b0100100;//2
  end
  5'b0_0011:
  begin
    led <= 18'b00_0000_0000_0000_1000;
    seg = 7'b0110000;//3
  end
  5'b0_0100:
  begin
    led <= 18'b00_0000_0000_0001_0000;
    seg <= 7'b0011001;//4
  end
  5'b0_0101:
  begin
    led <= 18'b00_0000_0000_0010_0000;
    seg <= 7'b0010010;//5
  end
  5'b0_0110:
  begin
    led <= 18'b00_0000_0000_0100_0000;
    seg <= 7'b0000010;//6
  end
  5'b0_0111:
  begin
    led <= 18'b00_0000_0000_1000_0000;
    seg <= 7'b1111000;//7
  end
  5'b0_1000:
  begin
    led <= 18'b00_0000_0001_0000_0000;
    seg <= 7'b0000000;//8
  end
  5'b0_1001:
  begin
    led <= 18'b00_0000_0010_0000_0000;
    seg <= 7'b0011000;//9
  end
  5'b0_1010:
  begin
    led <= 18'b00_0000_0100_0000_0000;
    seg <= 7'b0001000;//A
  end
  5'b0_1011:
  begin
    led <= 18'b00_0000_1000_0000_0000;
    seg <= 7'b0000011;//B
  end
  5'b0_1100:
  begin
    led <= 18'b00_0001_0000_0000_0000;
    seg <= 7'b1000110;//C
  end
  5'b0_1101:
  begin
    led <= 18'b00_0010_0000_0000_0000;
    seg <= 7'b0100001;//D
  end
  5'b0_1110:
  begin
    led <= 18'b00_0100_0000_0000_0000;
    seg <= 7'b0000110;//E
  end
  5'b0_1111:
  begin
    led <= 18'b00_1000_0000_0000_0000;
    seg = 7'b0001110;//F
  end
  5'b1_0000:
  begin
    led <= 18'b01_0000_0000_0000_0000;
    seg <= 7'b0001001;//H
  end
  5'b1_0001:
  begin
    led <= 18'b11_1111_1111_1111_1111; 
    seg <= 7'b1111111;//dark
  end
  default: 
  begin
    led <= 18'b00_0000_0000_0000_0001; //1
    seg <= 7'b0000000;//8
  end
  endcase
end
endmodule
//以下是编写的testbench文件
`timescale 1ns/1ns 
module led_tb; 
reg CLOCK_50M; 
reg RST_N; 
wire [17:0] LED;
wire [6:0] SEG;
led_flow led_inst 
( 
  .sys_clk(CLOCK_50M), 
  .rst_n(RST_N), 
  .led(LED),
  .seg(SEG)
  ); 
initial 
begin
  CLOCK_50M = 0; 
  while (1) 
  #10 CLOCK_50M = ~CLOCK_50M; 
end
initial
begin
  RST_N = 0; 
  while (1) 
  #10 RST_N = 1; 
end
initial
begin
  $display($time,"CLOCK_50M=%d RST_N=%d LED =%d", CLOCK_50M, RST_N, LED); 
end
endmodule 此帖出自小平头技术问答