如图所示，在verilog语句中用什么语句来吧几个模块连接起来呢？组装成一个整体大的模块，该大模块包含这些小模块。 就是类似于vhdl中的元件声明语句，最后在组装成一个整体大的模块。vhdl语句如下： LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS IS
  PORT(K:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
        EN:IN STD_LOGIC;
        RESET:IN STD_LOGIC;
        CLK:IN STD_LOGIC;
        Q:OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
END ENTITY DDS;
ARCHITECTURE ART OF DDS IS
  COMPONENT SUM99 IS
    PORT(K:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
          EN:IN STD_LOGIC;
          RESET:IN STD_LOGIC;
          CLK:IN STD_LOGIC;
          OUT1:OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
  END COMPONENT SUM99;
  COMPONENT REG1 IS
      PORT(D:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
          CLK:IN STD_LOGIC;
          Q:OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
  END COMPONENT REG1;
  COMPONENT ROM IS
    PORT(CLK:IN STD_LOGIC;
          ADDR:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
          OUTP:OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
  END COMPONENT ROM;
COMPONENT REG2 IS
    PORT(D:IN STD_LOGIC_VECTOR(8 DOWNTO 0);
          CLK:IN STD_LOGIC;
          Q:OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
  END COMPONENT REG2;
  SIGNAL S1:STD_LOGIC_VECTOR(9 DOWNTO 0);
  SIGNAL S2:STD_LOGIC_VECTOR(9 DOWNTO 0);
  SIGNAL S3:STD_LOGIC_VECTOR(8 DOWNTO 0);
  BEGIN
  U0:SUM99 PORT MAP(K=>K,EN=>EN,RESET=>RESET,CLK=>CLK,OUT1=>S1);
  U1:REG1 PORT MAP(D=>S1,CLK=>CLK,Q=>S2);
  U2:ROM PORT MAP(ADDR=>S2,CLK=>CLK,OUTP=>S3);
  U3:REG2 PORT MAP(D=>S3,CLK=>CLK,Q=>Q);
END ARCHITECTURE ART; 
此帖出自小平头技术问答