大家帮我看看下面的代码编译出错，问题找不出来，多谢指教 library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ; ENTITY RGBdianpingshiyan is   
   PORT (  
   CLK1      :IN  STD_LOGIC;
   RESET   :IN  STD_LOGIC;
   
   RO    :out    std_logic_vector(5 downto 0);
   GO    :out    std_logic_vector(5 downto 0);
   BO    :out    std_logic_vector(5 downto 0)
        );
END RGBdianpingshiyan;
-------------------------------------------------------------------------------
ARCHITECTURE arch OF RGBdianpingshiyan is
-------------------------------------------------------------------------------
signal V                   :STD_LOGIC_VECTOR(8 DOWNTO 0);
signal H                   :STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL read_enb:STD_LOGIC;
signal VSYNC          :STD_LOGIC;
signal HSYNC          :STD_LOGIC;
signal DE       :STD_LOGIC;
------------------------------------------------------------
constant  VS_Total_CLK     : integer  :=336; --Back Porch+VS_CLK+Front Porch ==qianlang(14)+320+houlang(2)
constant  HS_Total_CLK     : integer  :=736; --Back Porch+HS_CLK+Front Porch==qianlang(14)+720+houlang(2)
constant  vS_Back_Porch        : integer  :=14; --back porch =14.
constant  HS_Back_Porch        : integer  :=14; --back porch =14.
constant  VS_CLK      : integer  :=320;--320 --Panel Size VS 320*240
constant  HS_CLK      : integer  :=240;--240 --Panel Size HS
-------------------------------------------------------------------------------
BEGIN
------------------------------------------------------------------------------- PROCESS(CLK1)      --THIS BLOCK IS PRODUCE BASE CLK
BEGIN
 IF CLK1'EVENT AND CLK1='1' THEN
   IF (V=VS_Total_CLK AND H=HS_Total_CLK) THEN
    V <="000000000";
    H <="000000000";
   ELSIF H=HS_Total_CLK THEN
    V <=V+1;
    H <="000000000";
   ELSE
    H <=H+1;
   end if;
  else
   V <="000000000";
   H <="000000000";
 END IF;
END PROCESS;
-------------------------------------------------------------------------------
PROCESS(CLK1)               --VSYNC
BEGIN
 IF CLK1'EVENT AND CLK1='1' THEN
  IF (V=0 AND H=0) THEN
   VSYNC <='0';
  ELSIF (V=2 AND H=0) THEN  --3
   VSYNC <='1';
  END IF;
 END IF;
END PROCESS;
-------------------------------------------------------------------------------
PROCESS(CLK1)                --HSYNC
BEGIN
 IF RESET='0' THEN
  HSYNC <='0';
 ELSIF CLK1'EVENT AND CLK1='1' THEN
  IF H=0 THEN
   HSYNC <='0';
  ELSIF H=2 THEN
   HSYNC <='1';
  END IF;
 END IF;
END PROCESS;
-------------------------------------------------------------------------------
PROCESS(CLK1)                  --DE
BEGIN
 IF RESET='0' THEN
  DE <='1';
  read_enb <='1';
 ELSIF CLK1'EVENT AND CLK1='1' THEN
  IF V<VS_Back_Porch OR V >(VS_Back_Porch+VS_CLK) THEN  --Vsync Back Porch,(Vsync Back Porch+Vsync)
   READ_ENB <='1';
   DE <='1';
  ELSIF H=(HS_Back_Porch-1) THEN --> -1   
   READ_ENB <='0';
  ELSIF H=HS_Back_Porch THEN --> not add   
   DE <='0';
  ELSIF H=(HS_Back_Porch+HS_CLK-1) THEN  --> -1
   READ_ENB <='1';
  ELSIF H=(HS_Back_Porch+HS_CLK) THEN --> not add 
   DE <='1';
  END IF;
 END IF;
END PROCESS;
-------------------------------------------------------------------------------
PROCESS(CLK1)
Variable  HS_Back_Porch        : integer range 0 to 750 :=14; --back porch =14.
BEGIN
 IF RESET='0' THEN
  RO <="000000";
  GO <="000000";
  BO <="000000";
 ELSIF CLK1'EVENT AND CLK1='1' then -----Color Bar
   if h>=HS_Back_Porch and h< (HS_Back_Porch+30) then    --Red, 240/8=30
           RO <="111111";
           GO <="000000";
           BO <="000000"; 
   elsif h>= (HS_Back_Porch+30) and h <(HS_Back_Porch+60) then --Green
           RO <="000000";
           GO <="111111";
           BO <="000000";
   elsif h>= (HS_Back_Porch+60) and h <(HS_Back_Porch+90) then --Blue
           RO <="000000";
           GO <="000000";
           BO <="111111";
   elsif h>= (HS_Back_Porch+90) and h <(HS_Back_Porch+120) then --R&G
           RO <="111111";
           GO <="111111";
           BO <="000000";                                               
   elsif h>= (HS_Back_Porch+120) and h <(HS_Back_Porch+150) then --R&B
           RO <="111111";
           GO <="000000";
           BO <="111111";                                                         
   elsif h>= (HS_Back_Porch+150) and h <(HS_Back_Porch+180) then --G&B
           RO <="000000";
           GO <="111111";
           BO <="111111";                                               
   elsif h>= (HS_Back_Porch+180) and h <(HS_Back_Porch+210) then --White
           RO <="111111";
           GO <="111111";
           BO <="111111"; 
   elsif h>= (HS_Back_Porch+210) and h <(HS_Back_Porch+240) then --Black
           RO <="000000";
           GO <="000000";
           BO <="000000";                                                                  
   else        
           RO <="000000";
           GO <="000000";
           BO <="000000";
end if;
end if;  
END PROCESS;
-------------------------------------------------------------------------------
END Arch;     编译后出现： Error (10818): Can't infer register for "H[0]" at RGBdianpingshiyan.vhdl(39) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "H[1]" at RGBdianpingshiyan.vhdl(39) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "H[2]" at RGBdianpingshiyan.vhdl(39) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "H[3]" at RGBdianpingshiyan.vhdl(39) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "H[4]" at RGBdianpingshiyan.vhdl(39) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "H[5]" at RGBdianpingshiyan.vhdl(39) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "H[6]" at RGBdianpingshiyan.vhdl(39) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "H[7]" at RGBdianpingshiyan.vhdl(39) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "H[8]" at RGBdianpingshiyan.vhdl(39) because it does not hold its value outside the clock edge
Error (10822): HDL error at RGBdianpingshiyan.vhdl(39): couldn't implement registers for assignments on this clock edge 我不知道什么原因导致的H的值不确定，请大家帮忙看看，同样的问题存在与V。 此帖出自小平头技术问答