这是本人写的关于将视频解码后的YCbCr422中一帧图像的亮度信号Y保存到sram中，写完一帧后从sram读出进行后续分析的verilog HDL代码。现在的问题是输出的数据仅仅是最后一个数据，而地址却是逐渐累加的，没发现什么错误。希望高手们给分析一下，不胜感激！！！ VGA分辨率640*480  sram是256*16 的。最后可以帮忙改正一下。   module sram_c5(
  VGA_VS,
  VGA_HS,
  iclk,
  swit,
  Yw,
  sram_addr,
  sram_data,
  sram_oe_n,
  sram_ce_n,
  sram_we_n,
  sram_lb_n,
  sram_ub_n,
  led,
  sram_odata,
  );
input                  VGA_VS;
input                  VGA_HS; 
input[7:0]                 Yw;
input                    iclk;
output[17:0]        sram_addr;
inout[7:0]          sram_data;
input                    swit;
output  sram_oe_n,sram_ce_n,sram_we_n,sram_lb_n,sram_ub_n;
output[7:0]              led;
output[7:0]       sram_odata; wire               sram_oe_n1;
wire               sram_we_n1;
wire               sram_we_n2;
wire               sram_oe_n2;
wire                      con;
wire[7:0] sram_data,sram_idata,sram_odata;
wire[17:0] sram_addr1,sram_addr2; sram_wr sram_wr(
 .iclk(iclk),
 .Yw(Yw),
 .VGA_VS(VGA_VS),
 .VGA_HS(VGA_HS),
 .sram_data(sram_data),
 .swit(swit),
 .sram_oe_n1(sram_oe_n1),
 .sram_we_n1(sram_we_n1),
 .sram_addr1(sram_addr1),
 .con(con)
 );
sram_rd sram_rd(
    .swit(swit),
 .iclk(iclk),
 .sram_data(sram_data),
 .sram_odata(sram_odata),
 .led(led),
 .sram_oe_n2(sram_oe_n2),
 .sram_we_n2(sram_we_n2),
 .sram_addr2(sram_addr2),
 .con(con)
); assign sram_ce_n=0;
assign sram_lb_n=0;
assign sram_ub_n=1;
assign sram_addr=(!con)?sram_addr1:sram_addr2;
assign sram_oe_n=(!con)?sram_oe_n1:sram_oe_n2;
assign sram_we_n=(!con)?sram_we_n1:sram_we_n2;   endmodule       //       下面是写的模块 module sram_wr(
  sram_data,
  Yw,
  VGA_VS,
  VGA_HS,
  sram_addr1,
  iclk,   swit,
  sram_oe_n1,
  sram_we_n1,
  con     );
input                         iclk;
input[7:0]                  Yw;
output[17:0]        sram_addr1;
input                     swit;
input                   VGA_VS;
input                   VGA_HS;
output[7:0]           sram_data;
output   sram_oe_n1,sram_we_n1;
output                     con;
reg[7:0]               wr_data;
reg[17:0]               addr_r;
reg                 sram_we_n1;
reg                 sram_oe_n1;
//-----------------------下面的上升沿是为了检测一帧的开始------------------------------------------//
reg pluse_buf1;
reg pluse_buf2;
always @(posedge iclk)
begin
      pluse_buf1<= VGA_VS;
      pluse_buf2<=pluse_buf1;
end
assign   pluse_raise1 = pluse_buf1  & (~pluse_buf2);//-----------vs---------------     reg flag;
always@(posedge pluse_raise1) begin
 if(!swit) flag<=0;
 else begin
     if(VGA_VS) flag<=1;
   end
end  //-----------------------------------------------------     reg con;
always@(posedge iclk) begin
   if(!swit) begin
         wr_data<=8'd0;
         addr_r<=18'd0;
         con<=0;
         sram_we_n1<=1;
         sram_oe_n1<=1;
         end
   else if(!con) begin
           if(flag) begin
              if(VGA_VS) begin
                    if(VGA_HS) begin    
                      sram_we_n1<=0;
                      sram_oe_n1<=1;
                      addr_r<=addr_r+1;        
                      wr_data<=Yw;
                     end
                 end                                      
             else begin
                con<=1;
               end 
              
          end
           
     end
end assign sram_addr1=addr_r;
assign sram_data=(!sram_we_n1)?wr_data:8'hzz;
endmodule        下面是读的模块   module sram_rd(
  swit,
  sram_odata,
  sram_data,
  sram_addr2,
  iclk,
  con,
  sram_oe_n2,
  sram_we_n2,
  led
  );
input                       swit;
input                       iclk;
output[7:0]           sram_odata;
output[17:0]          sram_addr2;
input                        con;
input[7:0]             sram_data;
output     sram_oe_n2,sram_we_n2;
output[7:0]                  led;
 
reg[7:0]                 rd_data;
reg[17:0]                 addr_r;
reg                   sram_oe_n2;
wire                     VGA_4CLK;
reg[23:0]                     cnt1;
always@(posedge iclk)
cnt1<=cnt1+1;
assign VGA_4CLK=cnt1[23];
reg[17:0] cnt2;
always@(posedge VGA_4CLK) begin
   if(con&&swit) cnt2<=cnt2+1;
   else cnt2<=17'b0;
end
assign     sram_we_n2=1;
always@(posedge VGA_4CLK) begin
  if(con&&swit) begin
    if(cnt2<17'd47) begin
         sram_oe_n2<=0;
         addr_r<=cnt2;
         rd_data<=sram_data;
         end
    else  begin
         sram_oe_n2<=1;
         rd_data<=8'h0;    
         end
     end  
end assign sram_addr2=addr_r;
assign sram_odata=rd_data;
assign led=sram_odata; endmodule     
  此帖出自小平头技术问答