其实是一个比较简单的不同时区的时间转换的程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY srxs4 IS
PORT(clk1 , clk2 , clk3 , clk4 , clk5 ,clk9,clk8:IN STD_LOGIC;
dis_out1 , dis_out2 , dis_out3, dis_out4:out STD_LOGIC_VECTOR(4 DOWNTO 0));
END srxs4;
ARCHITECTURE sq OF srxs4 IS
BEGIN
PROCESS(clk1 , clk2 , clk3 , clk4 , clk5 , clk9,clk8)
variable i1 , i2, i3 ,i4 ,i5 ,a1, a2,b1,b2,c1,c2: integer :=0;
variable X1,X2,X3,X4:STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
IF (clk1='1') then
i1:=1;
else i1:=0;
end if;
IF (clk2='1') then
i2:=8;
else i2:=0;
end if;
IF (clk3='1') then
i3:=4;
else i3:=0;
end if;
IF (clk4='1') then
i4:=2;
else i4:=0;
end if;
IF (clk5='1') then
i5:=1;
else i5:=0;
end if;
if (clk9'event and clk9='1')then
a1:=i2 +i3+ i4 +i5;
CASE a1 IS
WHEN 0 => X2:="00000";--显示0 gfedcba
WHEN 1 => X2:="00001";--显示1
WHEN 2 => X2:="00010";--显示2
WHEN 3 => X2:="00011";--显示3
WHEN 4 => X2:="00100";--显示4
WHEN 5 => X2:="00101";--显示5
WHEN 6 => X2:="00110";--显示6
WHEN 7 => X2:="00111";--显示7
WHEN 8 => X2:="01000";--显示8
WHEN 9 => X2:="01001";--显示9
WHEN 10 => X2:="01010";--显示A
WHEN 11 => X2:="01011";--显示B
WHEN 12 =>X2:="01100";--显示C
WHEN OTHERS => X2:="00000";
END CASE;
if i1=1 then X1:="01110";
else X2:="10011";
end if;
c1:=i1; --记录第一次的东时区or西时区
b1:=a1; --记录第一次的时区
end if;
if (clk9'event and clk9='0')then
a2:=(i1*10+ i2 +i3+ i4 +i5);
CASE a2 IS
WHEN 0 =>X3:="00000";
X4:="00000";--显示00
WHEN 1 => X3:="00000";
X4:="00001";--显示01
WHEN 2 => X3:="00000";
X4:="00010";--显示02
WHEN 3 => X3:="00000";
X4:="00011";--显示03
WHEN 4 => X3:="00000";
X4:="00100";--显示04
WHEN 5 => X3:="00000";
X4:="00101";--显示05
WHEN 6 => X3:="00000";
X4:="00110";--显示06
WHEN 7 => X3:="00000";
X4:="00111";--显示07
WHEN 8 => X3:="00000";
X4:="01000";--显示08
WHEN 9 => X3:="00000";
X4:="01001";--显示09
WHEN 10 =>X3:="00001";
X4:="00000";--显示10
WHEN 11 =>X3:="00001";
X4:="00001";--显示11
WHEN 12 => X3:="00001";
X4:="00010";--显示12
WHEN 13 => X3:="00001";
X4:="00011";--显示13
WHEN 14 => X3:="00001";
X4:="00100";--显示14
WHEN 15 => X3:="00001";
X4:="00101";--显示15
WHEN 16 => X3:="00001";
X4:="00110";--显示16
WHEN 17 => X3:="00001";
X4:="00111";--显示17
WHEN 18 => X3:="00001";
X4:="01000";--显示18
WHEN 19 => X3:="00001";
X4:="01001";--显示19
WHEN 20 => X3:="00010";
X4:="00000";--显示20
WHEN 21 => X3:="00010";
X4:="00001";--显示21
WHEN 22 => X3:="00010";
X4:="00010";--显示22
WHEN 23 => X3:="00010";
X4:="00011";--显示23
WHEN 24 => X3:="00010";
X4:="00100";--显示24
WHEN OTHERS => X3:="00000";
X4:="00000";
END CASE;
b2:=a2; --记录第一次的时间
end if;
--第二次开始
IF clk8='1' then
IF (clk1='1') then
i1:=1;
else i1:=0;
end if;
IF (clk2='1') then
i2:=8;
else i2:=0;
end if;
IF (clk3='1') then
i3:=4;
else i3:=0;
end if;
IF (clk4='1') then
i4:=2;
else i4:=0;
end if;
IF (clk5='1') then
i5:=1;
else i5:=0;
end if;
if(clk9'event and clk9='1')then
a1:=i2 +i3+ i4 +i5;
CASE a1 IS
WHEN 0 => X2:="00000";--显示0 gfedcba
WHEN 1 => X2:="00001";--显示1
WHEN 2 => X2:="00010";--显示2
WHEN 3 => X2:="00011";--显示3
WHEN 4 => X2:="00100";--显示4
WHEN 5 => X2:="00101";--显示5
WHEN 6 => X2:="00110";--显示6
WHEN 7 => X2:="00111";--显示7
WHEN 8 => X2:="01000";--显示8
WHEN 9 => X2:="01001";--显示9
WHEN 10 => X2:="01010";--显示A
WHEN 11 => X2:="01011";--显示B
WHEN 12 =>X2:="01100";--显示C
WHEN OTHERS => X2:="00000";
END CASE;
if i1=1 then X1:="01110";
else X2:="10011";
end if;
dis_out1<=X1;
dis_out2<=X2;
end if;
--开始计算
if c1=1 then
if i1=1 then
c2:= b2+a1-b1;
else c2:=b2-b1-a1;
end if;
end if;
if c1=0 then
if i1=0 then
c2:= b2-(a1-b1);
else c2:=b2+b1+a1;
end if;
end if;
if c2>24 then c2:=c2-24;
end if;
if c2<0 then c2:=c2+24;
end if;
if (clk9'event and clk9='0')then
a2:=c2;
CASE a2 IS
WHEN 0 =>X3:="00000";
X4:="00000";--显示00
WHEN 1 => X3:="00000";
X4:="00001";--显示01
WHEN 2 => X3:="00000";
X4:="00010";--显示02
WHEN 3 => X3:="00000";
X4:="00011";--显示03
WHEN 4 => X3:="00000";
X4:="00100";--显示04
WHEN 5 => X3:="00000";
X4:="00101";--显示05
WHEN 6 => X3:="00000";
X4:="00110";--显示06
WHEN 7 => X3:="00000";
X4:="00111";--显示07
WHEN 8 => X3:="00000";
X4:="01000";--显示08
WHEN 9 => X3:="00000";
X4:="01001";--显示09
WHEN 10 =>X3:="00001";
X4:="00000";--显示10
WHEN 11 =>X3:="00001";
X4:="00001";--显示11
WHEN 12 => X3:="00001";
X4:="00010";--显示12
WHEN 13 => X3:="00001";
X4:="00011";--显示13
WHEN 14 => X3:="00001";
X4:="00100";--显示14
WHEN 15 => X3:="00001";
X4:="00101";--显示15
WHEN 16 => X3:="00001";
X4:="00110";--显示16
WHEN 17 => X3:="00001";
X4:="00111";--显示17
WHEN 18 => X3:="00001";
X4:="01000";--显示18
WHEN 19 => X3:="00001";
X4:="01001";--显示19
WHEN 20 => X3:="00010";
X4:="00000";--显示20
WHEN 21 => X3:="00010";
X4:="00001";--显示21
WHEN 22 => X3:="00010";
X4:="00010";--显示22
WHEN 23 => X3:="00010";
X4:="00011";--显示23
WHEN 24 => X3:="00010";
X4:="00100";--显示24
WHEN OTHERS => X3:="00000";
X4:="00000";
END CASE;
end if;
END IF;
dis_out1<=X1;
dis_out2<=X2;
dis_out3<=X3;
dis_out4<=X4;
END PROCESS ;
END sq;
可是一直出现
Error (10821): HDL error at srxs4.vhd(142): can't infer register for "X4[0]" because its behavior does not match any supported register model
这个问题，不知道是什么原因，求教一下。。。谢谢！
小弟是刚刚开始学，请多多包涵呐~
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上面意思说，X4[0]相关的寄存器不能综合，原因在于他的行为不匹配任何硬件可以支持的寄存器模型！
需要给你说明
在一个PROCESS的进程中只能有如下风格；
PROCESS(CLK,RST)
BGEGIN
IF (RST='1') THEN
NULL;
ELSIF CLK'EVENT AND CLK='1' THEN
-----------语句
END IF;
END PROCESS;
楼上的兄弟说的啥端口信号问题？
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