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这个帮你顶一下!

有ISE 了，还上来问这个问题！ISE上带这个语言的模本的，先给你一个自己看看，顺便自己找找这个代码怎么找。GOOGLE一下
Library UNISIM;
use UNISIM.vcomponents.all;

--  <-----Cut code below this line and paste into the architecture body---->

   -- DCM_SP: Digital Clock Manager Circuit
   --         Spartan-3E/3A
   -- Xilinx HDL Language Template, version 10.1

   DCM_SP_inst : DCM_SP
   generic map (
      CLKDV_DIVIDE => 2.0, --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
                           --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
      CLKFX_DIVIDE => 1,   --  Can be any interger from 1 to 32
      CLKFX_MULTIPLY => 4, --  Can be any integer from 1 to 32
      CLKIN_DIVIDE_BY_2 => FALSE, --  TRUE/FALSE to enable CLKIN divide by two feature
      CLKIN_PERIOD => 0.0, --  Specify period of input clock
      CLKOUT_PHASE_SHIFT => "NONE", --  Specify phase shift of "NONE", "FIXED" or "VARIABLE"
      CLK_FEEDBACK => "1X",         --  Specify clock feedback of "NONE", "1X" or "2X"
      DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or
                                             --     an integer from 0 to 15
      DFS_FREQUENCY_MODE => "LOW",     -- "HIGH" or "LOW" frequency mode for
                                       -- frequency synthesis
      DLL_FREQUENCY_MODE => "LOW",     -- "HIGH" or "LOW" frequency mode for DLL
      DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE
      FACTORY_JF => X"C080",          --  FACTORY JF Values
      PHASE_SHIFT => 0,        --  Amount of fixed phase shift from -255 to 255
      STARTUP_WAIT => FALSE) --  Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
   port map (
      CLK0 => CLK0,     -- 0 degree DCM CLK ouptput
      CLK180 => CLK180, -- 180 degree DCM CLK output
      CLK270 => CLK270, -- 270 degree DCM CLK output
      CLK2X => CLK2X,   -- 2X DCM CLK output
      CLK2X180 => CLK2X180, -- 2X, 180 degree DCM CLK out
      CLK90 => CLK90,   -- 90 degree DCM CLK output
      CLKDV => CLKDV,   -- Divided DCM CLK out (CLKDV_DIVIDE)
      CLKFX => CLKFX,   -- DCM CLK synthesis out (M/D)
      CLKFX180 => CLKFX180, -- 180 degree CLK synthesis out
      LOCKED => LOCKED, -- DCM LOCK status output
      PSDONE => PSDONE, -- Dynamic phase adjust done output
      STATUS => STATUS, -- 8-bit DCM status bits output
      CLKFB => CLKFB,   -- DCM clock feedback
      CLKIN => CLKIN,   -- Clock input (from IBUFG, BUFG or DCM)
      PSCLK => PSCLK,   -- Dynamic phase adjust clock input
      PSEN => PSEN,     -- Dynamic phase adjust enable input
      PSINCDEC => PSINCDEC, -- Dynamic phase adjust increment/decrement
      RST => RST        -- DCM asynchronous reset input
   );

   -- End of DCM_SP_inst instantiation

谢版主支持！

谢谢，这个是在unisim库中有例化的DCM模块，在调用是要怎么去例化它？

学习了, 好久没用ISE软件了!