module feq (clk,rst_n,clk100);
 input     clk,rst_n;
 output    clk100;
 reg       clk100;
 reg [6:0] cnt;
 always@(posedge clk)
 begin
 if(!rst_n)
 begin
  cnt<=7'b0;
  clk100<=1'b0;
 end
 else
  if(cnt==49)
 begin
  cnt<=7'b0;
  clk100<=~clk100;
 end
  else
 begin
  clk100<=clk100;
  cnt<=cnt+1;
 end
 end
endmodule       Warning (10230): Verilog HDL assignment warning at feq.v(22): truncated value with size 32 to match size of target (7)
Warning: No exact pin location assignment(s) for 3 pins of 3 total pins
 Info: Pin clk100 not assigned to an exact location on the device
 Info: Pin rst_n not assigned to an exact location on the device
 Info: Pin clk not assigned to an exact location on the device
Warning: Found 1 output pins without output pin load capacitance assignment
 Info: Pin "clk100" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Warning: Found pins functioning as undefined clocks and/or memory enables
 Info: Assuming node "clk" is an undefined clock 此帖出自小平头技术问答