entity Mux_4 is
port(input1,input2,input3,input4:in std_logic;
mux_1,mux_2: in std_logic;
mux_out
       
ut std_logic);
end Mux_4;



architecture Behavioral of Mux_4 is
signal sel : std_logic_vector(1 downto 0);

begin


process (mux_1,mux_2,input1,input2,input3,input4)
begin

sel <= mux_1 & mux_2;
case sel is
  when "00" => mux_out <= input1;
  when "01" => mux_out <= input2;
  when "10" => mux_out <= input3;
  when "11" => mux_out <= input4;
        when others => mux_out <= input1;
end case;
end process;

end Behavioral;



大家帮忙看看这段MUX4的代码，其输出mux_out的值应该是什么呢？？
仿真的时候，mux_out值是前一个时钟周期的值，
是不是因为进程语句，信号值在下次执行进程时才被更新，所以我的输出比输入延了一个周期呢？？？
此帖出自小平头技术问答