module ji(reset,clk,Oup,Odown,floor,shu);//panding shangsheng haishi xiajiang
input reset,clk,floor[0:7],shu[0:7];
output Oup,Odown;
reg Oup,Odown;
wire floor[0:7],shu[0:7];
integer a,b,i;
always @(reset or posedge clk)
begin
  a=0;b=0;
  for(i=0;i<=7;i=i+1)
  begin
  if(floor)
  a=a+2^i;
  if(shu)
  b=b+2^i;
  end
if(reset)begin
Oup<=0;
Odown<=0;end
else
begin
   if(b<a)
   begin
   Oup<=0;
   Odown<=1;
   end
   else if(b>a)begin
   Oup<=1;
   Odown<=0;end
   else begin
   Oup<=0;
   Odown<=0;end
   end
  end
  endmodule

Error (10773): Verilog HDL error at Verilog1.v(22): declaring module ports or function arguments with unpacked array types requires SystemVerilog extensions




又一个出现了相同问题
module men(reset,clk,close,open,topen,tclose,Oup,Odown);
input reset,clk,close,open,Oup,Odown;
output tclose,topen;
reg tclose,topen;
always @(reset or posedge clk)
begin
if(reset)begin
tclose<=1;
topen<=0;
end
else begin
  if((Oup==1)||(Odown==1)) begin
     tclose<=1;
     topen<=0;
     end
  else if((close==1)&&(open==0)) begin
      tclose<=1;
      topen<=0;
      end
      else if((close==0)&&(open==1)) begin
        tclose<=0;
        topen<=1;
        end
        else
        begin
          tclose<=0;
          topen<=1;
          end
         
end
end
endmodule


Error (10773): Verilog HDL error at Verilog1.v(22): declaring module ports or function arguments with unpacked array types requires SystemVerilog extensions 此帖出自小平头技术问答