1 姒傝堪         鏈疄渚嬮€氳繃PLL浜х敓鐨勪笉鍚岄鐜囩殑鏃堕挓锛屽垎鍒┍鍔?涓狶ED鎸囩ず鐏棯鐑佷竴鏍风殑棰戠巼銆傛湰瀹炰緥鐨勯噸鐐瑰叾瀹炰笉鏄疞ED锛岃€屾槸IP鏍哥殑搴旂敤锛屽綋鐒讹紝浠呬互PLL IP鏍镐负渚嬨€?/div> 2 妯″潡鍖栬璁?/font>         鍙傝€冩枃妗ｃ€婄帺杞琙ynq-鍩虹绡囷細鍩轰簬FPGA鐨勬ā鍧楀寲璁捐.pdf銆嬨€?/div> 3 PLL IP鏍告坊鍔犻厤缃?/font>    3.1Vivado鏍囧噯IP鏍告杩?/font>         鎴戜滑甯歌鐨処P鏍革紝涔熷氨鏄煡璇嗕骇鏉冿紙Intellectual Property锛夛紝鏄偅浜涘繁楠岃瘉鐨勩€佸彲閲嶅埄鐢ㄧ殑銆佸叿鏈夋煇绉嶇‘瀹氬姛鑳界殑璁捐鍔熻兘妯″潡銆侷P鏍镐竴鑸垎涓鸿蒋IP锛坰oft IP core锛夈€佸浐IP锛坒irm IP core锛夊拰纭琁P锛坔ard IP core锛夈€傝蒋IP鏄敤鏌愮楂樼骇璇█鏉ユ弿杩板姛鑳藉潡鐨勮涓猴紝浣嗘槸骞朵笉娑夊強鐢ㄤ粈涔堢數璺拰鐢佃矾鍏冧欢瀹炵幇杩欎簺琛屼负銆傚浐IP闄や簡瀹屾垚杞疘P鎵€鏈夌殑璁捐澶栵紝杩樺畬鎴愪簡闂ㄧ數璺骇缁煎悎鍜屾椂搴忎豢鐪熺瓑璁捐鐜妭锛屼竴鑸互闂ㄧ數璺骇缃戣〃褰㈠紡鎻愪氦鐢ㄦ埛浣跨敤銆傜‖IP鍒欐槸瀹屾垚浜嗙患鍚堢殑鍔熻兘鍧楋紝宸叉湁鍥哄畾鐨勬嫇鎵戝竷灞€鍜屽叿浣撳伐鑹猴紝骞跺繁缁忕粡杩囧伐鑹洪獙璇侊紝鍏锋湁鍙繚璇佺殑鎬ц兘銆傝璁℃繁搴︽剤娣憋紝鍚庣画宸ュ簭鎵€闇€瑕佸仛鐨勪簨鎯呭氨瓒婂皯锛屼絾鏄伒娲绘€т篃灏辫秺灏忋€?/div>         鍦╔ilinx鐨凢PGA鍣ㄤ欢涓紝IP鏍歌璁℃槸闈炲父閲嶈骞朵笖蹇呬笉鍙皯鐨勪竴閮ㄥ垎锛屽簲璇ヨ锛屽墠杩扮殑杞疘P銆佸浐IP鍜岀‖IP锛屽湪鎴戜滑Zstar鏉胯浇鐨刏ynq涓婇兘鑳藉鎵惧埌韪奖銆傝€屽浜嶸ivado鏉ヨ锛屽浜嶺ilinx鎴栬€呭叾绗笁鏂瑰悎浣滀紮浼存彁渚涚殑锛屽凡缁忛泦鎴愬湪Vivado宸ュ叿鐣岄潰涓緵璁捐鑰呰皟鐢ㄧ殑IP锛屾垜浠涓斿彲浠ョО涔嬩负鏍囧噯IP鏍革紱鑰屽浜嶸ivado鏈泦鎴愮殑锛岀涓夋柟鎴栬€呯敤鎴疯嚜宸卞紑鍙戣璁＄殑IP鏍革紝鎴戜滑鍒欑О涔嬩负鐢ㄦ埛鑷畾涔塈P鏍搞€?/div>         瀵逛簬Vivado涓泦鎴愮殑IP鏍革紝鍙互鐐瑰嚮Vivado鑿滃崟Window --> IP Catalog鏌ョ湅銆?/div>          鍦╒ivado涓昏绐椾腑锛孖P Catalog --> Cores涓紝鍒楀嚭浜哣ivado宸茬粡闆嗘垚鐨勫垎绫籌P鏍革紝鐐瑰嚮鍚勪釜鍒嗙被鍓嶇殑+鍙凤紝鍙互鏌ョ湅鍏蜂綋鍒嗙被涓嬮兘鏈夊摢浜涘彲鐢ㄧ殑IP鏍搞€?/div>          瀵逛簬涓€鑸殑IP鏍革紝鍏堟壘鍒版墍闇€瑕佺殑IP鏍革紝鐒跺悗鍙屽嚮IP鏍稿脊鍑洪厤缃〉闈紝閰嶇疆瀹屾垚鍚庤緭鍑哄悇绫籌P鏍哥浉鍏宠璁℃枃浠讹紝鍦ㄧ敤鎴疯璁′腑鍙渚嬪寲IP鏍告ā鍧楀氨鍙互浜嗐€?/div>          涓嬮潰鎴戜滑浠star_ex04瀹炰緥鐨凱LL IP鏍哥殑閰嶇疆涓轰緥锛岀湅鐪嬪浣曟坊鍔犻厤缃甐ivado涓泦鎴愮殑鏍囧噯IP鏍搞€?/div> 3.2 PLL IP鏍搁厤缃疄渚?/font>         濡傚浘鎵€绀猴紝鐐瑰嚮Flow Navigator闈㈡澘涓嬬殑鈥淧roject Manager 脿 IP Catalog鈥濄€?/div> 鍥?IP Catalog鑿滃崟         濡傚浘鎵€绀猴紝寮瑰嚭鐨処P Catalog闈㈡澘涓垪鍑轰簡鎵€鏈塚ivado鑷甫IP鏍哥殑鍒嗙被鍒楄〃銆?/div> 鍥?IP Catalog闈㈡澘         濡傚浘鎵€绀猴紝鍦ㄢ€淔PGA Features and Design 脿 Clocking鈥濆垎绫诲睍寮€鍚庯紝鍙互鐪嬪埌鍚嶄负Clocking Wizard鐨処P鏍革紝閫氳繃杩欎釜IP鏍革紝鎴戜滑鍙互閰嶇疆涓€涓狿LL鐢ㄤ簬瀵笷PGA澶栭儴杈撳叆鏃堕挓鍋氬悇绉嶅垎棰戞垨鍊嶉澶勭悊銆傜偣鍑籆locking Wizard鍚庡皢寮瑰嚭鐩稿簲鐨勯厤缃〉闈€?/div> 鍥?Clocking Wizard IP鏍?/div>         寮瑰嚭鐨勭涓€涓厤缃〉闈㈠鍥炬墍绀猴紝杩欓噷鐨凱rimitive鍙互閫夋嫨鈥淧LL鈥濓紝鐒跺悗鍦ㄦ椂閽熼鐜囷紙Input Clock Information锛夌殑Primary涓€琛屼腑璁惧畾鎴戜滑鐨勮緭鍏ユ椂閽熼鐜囷紙Input Frequency锛変负25MHz鍗冲彲銆?/div> 鍥?Clocking Options閰嶇疆椤甸潰         鎺ョ潃鍦∣utput Clocks閰嶇疆椤甸潰涓紝濡傚浘鎵€绀猴紝鍕鹃€塩lk_out1/2/3杩?涓椂閽燂紝鍒嗗埆璁剧疆鍏惰緭鍑洪鐜囦负25MHz銆?0MHz銆?00MHz銆傚悓鏃跺嬀閫夋帶鍒朵俊鍙穜eset鍜宭ocked鐨勶紝骞朵笖瀹冧滑鏄珮鐢靛钩鏈夋晥锛圓ctive High锛夈€?/div> 鍥?Output Clocks閰嶇疆椤甸潰         鎺ヤ笅鏉ュ嚑涓〉闈笉闇€瑕佸仛閰嶇疆鏇存敼锛岀洿鎺ョ偣鍑籓K瀹屾垚PLL鐨勯厤缃€?/div>         閰嶇疆鐢熸晥鍚庯紝鎴戜滑鍙互鍒囨崲鍒癝ources闈㈡澘涓嬫柟鐨処P Sources杩欎釜瀛愰〉闈腑锛屽鍥炬墍绀猴紝鍑虹幇浜嗗悕涓篶lk_wiz_0鐨処P鏍革紝鍗虫垜浠垰鍒氶厤缃坊鍔犵殑IP鏍搞€傚彲浠ョ偣鍑诲睍寮€瀹冿紝鍦ㄢ€淚nstantiation Template鈥濅笅鏂圭殑鈥渃lk_wiz_0.veo鈥濇枃浠跺氨鏄緥鍖栨ā鏉匡紝鍙互鍙屽嚮鎵撳紑瀹冦€?/div> 鍥?鏌ョ湅渚嬪寲妯℃澘         濡傚浘鎵€绀猴紝鍙互澶嶅埗杩欎釜PLL鐨勪緥鍖栨ā鏉匡紝鍦ㄦ垜浠殑宸ョ▼涓浉搴斾慨鏀瑰閮ㄦ帴鍙ｃ€?/div> 鍥?PLL渚嬪寲妯℃澘         鍏充簬杩欓噷PLL妯″潡鐨勬帴鍙ｅ畾涔夊琛ㄦ墍绀恒€?/div>  淇″彿鍚?/strong>  鏂瑰悜鍔熻兘鎻忚堪clk_in1杈撳叆PLL妯″潡鐨勮緭鍏ユ椂閽熶俊鍙凤紝鍗虫墍鏈夎緭鍑烘椂閽熺殑鍩洪銆?/div>clk_out1杈撳嚭PLL妯″潡鐨勮緭鍑烘椂閽?銆?/div>clk_out2杈撳嚭PLL妯″潡鐨勮緭鍑烘椂閽?銆?/div>clk_out3杈撳嚭PLL妯″潡鐨勮緭鍑烘椂閽?銆?/div>reset杈撳叆PLL妯″潡鐨勮緭鍏ュ浣嶄俊鍙凤紝楂樼數骞虫湁鏁堛€?/div>locked杈撳嚭PLL鐨勯攣瀹氭寚绀轰俊鍙凤紝楂樼數骞虫湁鏁堛€傚嵆璇ヤ俊鍙烽珮鐢靛钩鏃讹紝琛ㄧずPLL杈撳嚭鏃堕挓閮藉凡缁忔甯歌緭鍑恒€?/div>