PCB File : Documentsmotor4.PCB
Date     : 26-Apr-2013
Time     : 20:47:52

Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (On the board )
   Violation         Via (173mil,832mil) TopLayer to BottomLayer  Actual Hole Size = 157.48mil
   Violation         Via (4393mil,832mil) TopLayer to BottomLayer  Actual Hole Size = 157.48mil
   Violation         Via (4393mil,3267mil) TopLayer to BottomLayer  Actual Hole Size = 157.48mil
   Violation         Via (173mil,3267mil) TopLayer to BottomLayer  Actual Hole Size = 157.48mil
Rule Violations :4

Processing Rule : Clearance Constraint (Gap=8mil) (On the board ),(On the board )
Rule Violations :0

Processing Rule : Broken-Net Constraint ( (On the board ) )
   Violation         Net GND   is broken into 9 sub-nets. Routed To 83.67%
     Subnet : U705-9   Ca4-1    U705-11  U705-13  U705-15  U708-7   CP4-2    U7-15    J6-2     CR1-2   
              D12-2    R17-1    J18-6    J18-12   R22-2    R15-1    Ca5-2    C33-2    R21-2    U8-4     C2-2     
              J3-2     Q2-2     C1-2     U403-6   U403-3   C432-2   D431-1   U403-5   U1-35    CP3-2    U1-21   
              C18-1    CT2-2    C431-2   CT1-2    C430-2   S2-2     
     Subnet : R18-1   
     Subnet : R16-1   
     Subnet : R19-2   
     Subnet : R20-2   
     Subnet : CD1-2    CD2-1    U1-6     CR3-2   
     Subnet : U1-47   
     Subnet : CY1-2    CY2-2   
     Subnet : CR2-2
   Violation         Net DOUTA2   is broken into 2 sub-nets. Routed To 50.00%
     Subnet : U705-12  D14-2   
     Subnet : J7-2     
   Violation         Net DOUTA3   is broken into 2 sub-nets. Routed To 50.00%
     Subnet : U705-14  D23-2   
     Subnet : J7-3     
Rule Violations :3

Processing Rule : Short-Circuit Constraint (Allowed=Not Allowed) (On the board ),(On the board )
Rule Violations :0

Processing Rule : Width Constraint (Min=7mil) (Max=50mil) (Prefered=30mil) (On the board )
Rule Violations :0


Violations Detected : 7
Time Elapsed        : 00:00:05


不知道哪个错了。。一点都看不懂，麻烦看的懂的帮我讲下   谢谢了！