FPGA

DDR ERROR: tRFC violation during Activate bank 0

2020-02-02 10:24发布

站内问答 / FPGA
4588 1 1
# At time 273990.000 ns PRE  : Addr[10] = 1, Bank = 00
# At time 274020.000 ns AREF : Auto Refresh
# At time 274100.000 ns ACT  : Bank = 0, Row = Z000
# At time 274100.000 ns ERROR: tRFC violation during Activate bank 0
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