IOC (12 '' POS IN FEED_OR);
IOC (13 'ALARM' POS OUTCOM FEED_OR);
IOC (14 'TMR1_2_G' POS OUTCOM FEED_OR);
IOC (15 'CNT_RDY' POS OUTREG FEED_REG);
IOC (16 'CNT_ST' POS OUTREG FEED_REG);
IOC (17 '' POS IN FEED_OR);
IOC (18 'TMR0_CLK' POS OUTCOM FEED_OR);
IOC (19 'CLK_OUT' POS OUTCOM FEED_OR);
推荐用altera的epm7032s 5v电源,44条腿
用quartusⅡ来开发,数字电路可以画原理图,也可以用vhdl语言开发
请教一个问题,下面这一段代码用verilog是表示什么意思?
PEEL18CV8
AR node 21;
SP node 22;
CLK pin 1;
FREQ_DUT pin 2;
XTAL_8M pin 3;
EN_TMR12 pin 4;
CNTR_DLY pin 5;
TEST_ADJ pin 6;
TMR2_OUT pin 7;
TMR0_OUT pin 8;
EN_ALARM pin 9;
HI_FREQ pin 11;
IOC (12 '' POS IN FEED_OR);
IOC (13 'ALARM' POS OUTCOM FEED_OR);
IOC (14 'TMR1_2_G' POS OUTCOM FEED_OR);
IOC (15 'CNT_RDY' POS OUTREG FEED_REG);
IOC (16 'CNT_ST' POS OUTREG FEED_REG);
IOC (17 '' POS IN FEED_OR);
IOC (18 'TMR0_CLK' POS OUTCOM FEED_OR);
IOC (19 'CLK_OUT' POS OUTCOM FEED_OR);
Equations
AR = !CNTR_DLY;
ALARM.COM = TMR0_OUT & !TMR2_OUT & EN_ALARM;
TMR1_2_G.COM = EN_TMR12 & !CNTR_DLY #
TEST_ADJ & !CNTR_DLY #
CNTR_DLY & CNT_ST & !CNT_RDY;
CNT_RDY.D = EN_TMR12 & CNT_ST;
CNT_ST.D = EN_TMR12;
TMR0_CLK.COM = FREQ_DUT & HI_FREQ #
XTAL_8M & !HI_FREQ;
CLK_OUT.COM = TMR0_OUT & HI_FREQ #
FREQ_DUT & !HI_FREQ;
SP = 0;
这不是verilog,貌似叫别的名字,类似AHDL,忘了。
IOC是管脚定位?但印象里不是这个语法,应当是LOC。。。。不敢确定。。。
其他就是组合逻辑,&、#、!分别是与、或、非。
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