记得在2010年9月参加电子设计竞赛的时候，出现过这样的一个问题，我们需要一个拨码开关来实现数据的切换，可是在实现拨码开关读取的时候出现了一个问题了。很纠结的问题。ERROR:Place:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /
   clock site pair. The clock component  is placed at site . The IO component
   is placed at site .  This will not allow the use of the fast path between the IO and the Clock buffer.

当时也没有别人来帮助学习FPGA，所以这个算是自己学习了。很纠结的一件事情了，在百度上搜索了很长时间也无法没有找到，（其实在后来才知道这叫全局时钟约束到普通引脚上的问题，当时是个菜鸟，所以请大家原谅）。不过后来在google上面发了这样的话，
ERROR:Place:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB / clock site pair. The clock component <CLK16_inst> is placed at site <BUFGMUX_X0Y3>. The IO component <Ref_Clk_p> is placed at site <A8>.  This will not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule. < NET "Ref_Clk_p" CLOCK_DEDICATED_ROUTE = FALSE; >
原来问题是可以这样解决的，在约束条件上加入这句话就可以了
< NET "Ref_Clk_p" CLOCK_DEDICATED_ROUTE = FALSE; >
都怪自己粗心大意，没有好好学习了！

后来在学习数码管的学习中，又发现数码管竟然不亮，其实是计数没有做好，好纠结呀。只有自己慢慢琢磨其中的学习方法了，这个倒是不难，解决了计数问题就好办多了。。。。。。。。。。。。。。。。。。。。

慢慢的逐步进入了FPGA的学习中，虽然还没有摆脱菜鸟的水平，但是我相信我会succes的。