// CONFIG1L
/*----------------------------------------------------------------
VREG Sleep Enable bit (Ultra low-power
regulator is Disabled (Controlled by REGSLP bit))
------------------------------------------------------------------*/
#pragma config RETEN = OFF
/*----------------------------------------------------------------
LF-INTOSC Low-power Enable bit (LF-INTOSC
in High-power mode during Sleep)
------------------------------------------------------------------*/
#pragma config INTOSCSEL = HIGH
/*----------------------------------------------------------------
SOSC Power Selection and mode
Configuration bits (High Power SOSC circuit selected)
------------------------------------------------------------------*/
#pragma config SOSCSEL = HIGH
#pragma config XINST = OFF // Extended Instruction Set (Enabled)
// CONFIG2L
#pragma config PWRTEN = ON // Power Up Timer (Disabled)
/*----------------------------------------------------------------
Brown Out Detect (Enabled in hardware,
SBOREN disabled)
------------------------------------------------------------------*/
#pragma config BOREN = SBORDIS
#pragma config BORV = 0 // Brown-out Reset Voltage bits (1.8V)
/*----------------------------------------------------------------
BORMV Power level (ZPBORMV instead of
BORMV is selected)
------------------------------------------------------------------*/
#pragma config BORPWR = HIGH
// CONFIG2H
/*----------------------------------------------------------------
Watchdog Timer (WDT disabled in hardware;
SWDTEN bit disabled)
------------------------------------------------------------------*/
#pragma config WDTEN = OFF
#pragma config WDTPS = 1048576 // Watchdog Postscaler (1:1048576)
// CONFIG3H
/*----------------------------------------------------------------
ECAN Mux bit (ECAN TX and RX pins are
located on RB2 and RB3, respectively)
------------------------------------------------------------------*/
#pragma config FOSC =???
#pragma config WDT = OFF
// CONFIG1L
/*----------------------------------------------------------------
VREG Sleep Enable bit (Ultra low-power
regulator is Disabled (Controlled by REGSLP bit))
------------------------------------------------------------------*/
#pragma config RETEN = OFF
/*----------------------------------------------------------------
LF-INTOSC Low-power Enable bit (LF-INTOSC
in High-power mode during Sleep)
------------------------------------------------------------------*/
#pragma config INTOSCSEL = HIGH
/*----------------------------------------------------------------
SOSC Power Selection and mode
Configuration bits (High Power SOSC circuit selected)
------------------------------------------------------------------*/
#pragma config SOSCSEL = HIGH
#pragma config XINST = OFF // Extended Instruction Set (Enabled)
// CONFIG1H
/*----------------------------------------------------------------
Oscillator (HS oscillator (Medium power, 4
MHz - 16 MHz))
------------------------------------------------------------------*/
#pragma config FOSC = HS1
//#pragma config FOSC = INTIO2
#pragma config PLLCFG = ON // PLL x4 Enable bit (Enabled)
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor (Disabled)
/*----------------------------------------------------------------
Internal External Oscillator Switch Over
Mode (Disabled)
------------------------------------------------------------------*/
#pragma config IESO = OFF
// CONFIG2L
#pragma config PWRTEN = ON // Power Up Timer (Disabled)
/*----------------------------------------------------------------
Brown Out Detect (Enabled in hardware,
SBOREN disabled)
------------------------------------------------------------------*/
#pragma config BOREN = SBORDIS
#pragma config BORV = 0 // Brown-out Reset Voltage bits (1.8V)
/*----------------------------------------------------------------
BORMV Power level (ZPBORMV instead of
BORMV is selected)
------------------------------------------------------------------*/
#pragma config BORPWR = HIGH
// CONFIG2H
/*----------------------------------------------------------------
Watchdog Timer (WDT disabled in hardware;
SWDTEN bit disabled)
------------------------------------------------------------------*/
#pragma config WDTEN = OFF
#pragma config WDTPS = 1048576 // Watchdog Postscaler (1:1048576)
// CONFIG3H
/*----------------------------------------------------------------
ECAN Mux bit (ECAN TX and RX pins are
located on RB2 and RB3, respectively)
------------------------------------------------------------------*/
#pragma config CANMX = PORTB
/*----------------------------------------------------------------
MSSP address masking (7 Bit address
masking mode)
------------------------------------------------------------------*/
#pragma config MSSPMSK = MSK7
#pragma config MCLRE = OFF // Master Clear Enable (MCLR Enabled, RE3 Disabled)
// CONFIG4L
#pragma config STVREN = ON // Stack Overflow Reset (Enabled)
#pragma config BBSIZ = BB2K // Boot Block Size (2K word Boot Block size)
接了,,10uf 测量电压约3.2v
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