由于电路设计错误，在设计LCMXO3L-6900C-6BG256C的时候,
DCK引脚使用了A9引脚.
刚刚编译发现了一堆错误:
ERROR - Cannot place PIO comp "DCK" on PIO site "A9/PT22C" (I/O bank 0).
ERROR - Cannot place PIO comp "DCK" on the proposed PIO site "PT22C / A9" because the types of their IOLOGICs are incompatible:
the associated IOLOGIC comp "DCK_MGIOL" has been set to "ODDR4" mode (of type "TIOLOGIC"), while the IOLOGIC site is of type "TSIOLOGIC".
ERROR - Please check the pin locking in your preference file.
其实只要不用A9,其他的引脚都可以的，:'(
现在看来有两个办法：
1）重新设计，投板.....
2）有没有办法把oddr的输出通过内部布线连接到A9呢，哪位高手有建议？
环境是Lattice diamond 3.7
友情提示: 此问题已得到解决，问题已经关闭,关闭后问题禁止继续编辑，回答。
{var%20f='http://v.t.sina.com.cn/share/share.php?appkey=1515056452',u=z||d.location,p=['&url=',e(u),'&title=',e(t||d.title),'&source=',e(r),'&sourceUrl=',e(l),'&content=',c||'gb2312','&pic=',e(p||'')].join('');function%20a(){if(!window.open([f,p].join(''),'mb',['toolbar=0,status=0,resizable=1,width=440,height=430,left=',(s.width-440)/2,',top=',(s.height-430)/2].join('')))u.href=[f,p].join('');};if(/Firefox/.test(navigator.userAgent))setTimeout(a,0);else%20a();})(screen,document,encodeURIComponent,'','','https://www.xiaopingtou.cn/data/attach/logo/logo.png', '推荐 net_wolf 的问题《FPGA的ODDR输出引脚问题》','https://www.xiaopingtou.net/q-170038.html','页面编码gb2312|utf-8默认gb2312'));){kind=link}
The HS data signals (D0, D1, D2, D3) for the RX and TX D-PHY IP's should only use A/B IO pairs.
可能同样的限制也适用于 DCK.
另加一句:这里还是有点冷清啊，还是eevblog热闹多了...
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