悬赏现金解决时钟同步的问题

1楼-- · 2020-02-06 14:00

本帖最后由 feihufuture 于 2015-12-10 18:30 编辑

我共享一下我的哈：data 是外部设备输入的500Hz, clki1是本设备40M振荡器分频得到的8MHz输入，clki2r 是经过同步算法得到的1MHz时钟，clk500hz 是对clki2r分频后的500Hz输出，经验证，clk500hz与data同步的性能不是很好。@21ic小喇叭小美女，来帮忙顶下，有money
      always @ (posedge clki1 or negedge rst)
      begin
      if (!rst) data_r  <= 1'b0 ;
      else data_r  <= data ;
      end
   reg clk500hz;
      reg [13:0] Count = 10'b0;
      parameter Ktop = 14'd7000;
      //DPD
      wire dnup = clk500hz ^ data_r ;
      //DLF
      always @ (posedge clki1)
      begin
            if(!rst) Count<=0;
            else if(!dnup)
                     begin
                     if(Count == Ktop) Count <= 14'b0;
                     else Count <= Count + 1;
                     end
            else
                     begin
                     if(Count == 0) Count <= Ktop;
                     else Count <= Count - 1;
                     end
      end
      assign insert = (!dnup) & (Count == Ktop);
      assign deduct = dnup & (Count==0);
      //DCO

      always @ ( posedge clki1 or negedge rst )
      if ( !rst )
            start_point <= 3'd3 ;
      else if ( insert )
            start_point <= start_point + 1'b1 ;
      else if ( deduct )
            start_point <= start_point - 1'b1 ;
      else
            start_point <= start_point ;

      always @ ( posedge clki1 or negedge rst )
      if ( !rst )
            cnt <= 3'd0 ;
      else
            cnt <= cnt + 1'b1 ;

      always @ ( posedge clki1 or negedge rst )
      if ( !rst )
            clki2r <= 1'b0 ;
      else if( cnt ==  start_point )
            clki2r <= 1'b1 ;
      else if( cnt ==  start_point + 3'd4 )
            clki2r <= 1'b0 ;
      else
            clki2r <= clki2r ;

      //***************************************
      //clki2r is 1MHz clock
      reg [9:0] clk500hz_cnt1000;
      always @ ( posedge clki2r or negedge rst )
      begin
      if ( !rst ) clk500hz_cnt1000 <= 10'b0;
      else if(clk500hz_cnt1000 == 10'd999) clk500hz_cnt1000 <= 10'b0;
      else clk500hz_cnt1000 <= clk500hz_cnt1000 + 1;
      end


      //clk500hz
      assign clk500hz_o = clk500hz;
      always @ ( posedge clki2r or negedge rst )
      begin
      if ( !rst ) clk500hz <= 1'b0;
      else if(clk500hz_cnt1000 == 10'd999) clk500hz <= ~clk500hz;
      end