本帖最后由 pszcmzcm 于 2015-6-29 12:40 编辑

新人求助schematic 综合的一点问题
在综合后 technology schematic中 有数个LUT（如图所示）感觉没有意义属于资源浪费


EDA为ISE14.7


truetable为
input  output
0        0
1        1

考虑了一下应该是VHDL编写上的问题，大学中虽然涉及了FPGA 也 在Tutorial 中 学了基本的VHDL编写，但对于此类问题还是感觉无从下手，现在自学并为Msc准备中，希望大牛能告知一下解决方法和原理

code为简单的双向交通灯（FSM based)
具体如下：

1. library IEEE;
   
2. use IEEE.STD_LOGIC_1164.ALL;
   
3. 
   
4. entity Traffic_light is
   
5. 
   
6. port(clk:in std_logic;
   
7.           Test: in std_logic;
   
8.           Standby:in std_logic;
   
9.           R1,Y1,G1:out std_logic;
   
10.           R2,Y2,G2:out std_logic);
    
11.                   
    
12. end Traffic_light;
    
13. 
    
14. architecture Behavioral of Traffic_light is
    
15. 
    
16. 
    
17. constant time_max  :integer := 2700;
    
18. --The frequency of Clk is 60Hz--
    
19. constant time_RG   :integer := 1800;  
    
20. --time of light change from red & green(s)--
    
21. constant time_RY   :integer := 300;
    
22. --time of light change from red & yellow(s)--
    
23. constant time_GR   :integer := 2700;
    
24. --time of light change from green & red(s)--
    
25. constant time_YR   :integer := 300;
    
26. --time of light change from yellow & red(s)--
    
27. constant time_test :integer := 60;
    
28. --time for test mode(s)--
    
29. 
    
30. type state is (state_RY,state_GR,state_YR,state_RG,state_YY);
    
31. signal Pr_state,Nx_state: state;
    
32. signal time: integer range 0 to time_max;
    
33. 
    
34. begin
    
35. --lower section of state machine--
    
36. process(clk,standby)
    
37.         variable count: integer range 0 to time_max;
    
38.         begin
    
39.         if (standby = '1') then
    
40.                 Pr_state <= state_yy;
    
41.         elsif (clk'event and clk= '1') then
    
42.                 count := count +1;
    
43.                 if (count = time ) then
    
44.                 Pr_state <= Nx_state;
    
45.                 count := 0;
    
46.                 end if;
    
47.         end if;
    
48. end process;
    
49. 
    
50. --upper section of state machine--
    
51. process(pr_state,test)
    
52.         begin
    
53.         case pr_state is
    
54.         --state_RY--
    
55.         when state_RY =>
    
56.         R1 <= '1'; G1 <= '0'; Y1 <= '0';
    
57.         R2 <= '0'; G2 <= '0'; Y2 <= '1';
    
58.         Nx_state <= state_GR;
    
59.         if (test = '0') then time <= time_RY;
    
60.         else time <= time_test;
    
61.         end if;
    
62.         --state_GR--
    
63.         when state_GR =>
    
64.         R1 <= '0'; G1 <= '1'; Y1 <= '0';
    
65.         R2 <= '1'; G2 <= '0'; Y2 <= '0';
    
66.         Nx_state <= state_YR;
    
67.         if (test = '0') then time <= time_GR;
    
68.         else time <= time_test;
    
69.         end if;
    
70.         --state_YR--
    
71.         when state_YR =>
    
72.         R1 <= '0'; G1 <= '0'; Y1 <= '1';
    
73.         R2 <= '1'; G2 <= '0'; Y2 <= '0';
    
74.         Nx_state <= state_RG;
    
75.         if (test = '0') then time <= time_YR;
    
76.         else time <= time_test;
    
77.         end if;
    
78.         --state_RG--
    
79.         when state_RG =>
    
80.         R1 <= '1'; G1 <= '0'; Y1 <= '0';
    
81.         R2 <= '0'; G2 <= '1'; Y2 <= '0';
    
82.         Nx_state <= state_RY;
    
83.         if (test = '0') then time <= time_RG;
    
84.         else time <= time_test;
    
85.         end if;
    
86.         when others =>
    
87.         R1 <= '0'; G1 <= '0'; Y1 <= '1';
    
88.         R2 <= '0'; G2 <= '0'; Y2 <= '1';
    
89.         Nx_state <= state_RY;
    
90.         end case;
    
91. end process;
    
92. end Behavioral;

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