Verilog的按键消抖与松手检测如何做到，求给个思路

1楼-- · 2020-02-23 14:26

module remove
(
input rst_n,
input clk,//64KHz
input in,
output reg out
);
parameter CNT_WITDH = 8;
parameter THRESHOLD = 192;

reg [CNT_WITDH:0] cnt;
reg state;

always @( posedge clk or negedge rst_n )
      if ( !rst_n )
      begin
         state <= 1'b0;
         cnt <= 0;
      end
      else
         case(state)
         1'b0:begin
                  if(in==0)
                  begin
                        state <= 1'b1;
                        cnt <= 0;
                  end
                  else
                  begin
                        state <= 1'b0;
                        if(cnt<THRESHOLD)cnt <= cnt+1;
                  end
               end
         1'b1:begin
                  if(in==0)
                  begin
                        state <= 1'b1;
                        if(cnt<THRESHOLD) cnt <= cnt+1;
                  end
                  else
                  begin
                        state <= 1'b0;
                        cnt <= 0;
                  end
               end
         endcase

always @( posedge clk or negedge rst_n )
   if ( !rst_n )
      out <= 1;
   else if (cnt==THRESHOLD-1)
      out <= in;
endmodule

pianran

2楼-- · 2020-02-23 20:00

上面就是一个简单的去抖动程序。
时钟的频率和去除抖动的时间自己根据产品实际确定。
程序的思路简而言之，如果输入电平改变，就开始计数器计数，只有到达一定时间才认为是真正的变化，这时候输出才随之变化；否则就认为是抖动，输出保持不变。

jomanliang

3楼-- · 2020-02-24 00:23

module debounce_module
(
CLK, RSTn, Pin_In, Pin_Out
);

   input CLK;
   input RSTn;
   input Pin_In;
   output Pin_Out;

   /**************************/

   wire H2L_Sig;
   wire L2H_Sig;

   detect_module U1
   (
      .CLK( CLK ),
   .RSTn( RSTn ),
   .Pin_In( Pin_In ), // input - from top
   .H2L_Sig( H2L_Sig ), // output - to U2
   .L2H_Sig( L2H_Sig )  // output - to U2
   );

   /**************************/

   delay_module U2
   (
      .CLK( CLK ),
   .RSTn( RSTn ),
   .H2L_Sig( H2L_Sig ), // input - from U1
   .L2H_Sig( L2H_Sig ), // input - from U1
   .Pin_Out( Pin_Out )  // output - to top
   );

   /*******************************/

endmodule

module detect_module
(
CLK, RSTn, Pin_In, H2L_Sig, L2H_Sig
);

input CLK;
   input RSTn;
   input Pin_In;
   output H2L_Sig;
   output L2H_Sig;

   /**********************************/

   parameter T100US = 11'd1999;

   /**********************************/

   reg [10:0]Count1;
   reg isEn;

   always @ ( posedge CLK or negedge RSTn )
      if( !RSTn )
      begin
            Count1 <= 11'd0;
            isEn <= 1'b0;
end
      else if( Count1 == T100US )
isEn <= 1'b1;
   else
      Count1 <= Count1 + 1'b1;

/********************************************/

   reg H2L_F1;
   reg H2L_F2;
   reg L2H_F1;
   reg L2H_F2;

   always @ ( posedge CLK or negedge RSTn )
      if( !RSTn )
      begin
      H2L_F1 <= 1'b1;
   H2L_F2 <= 1'b1;
   L2H_F1 <= 1'b0;
   L2H_F2 <= 1'b0;
   end
   else
      begin
   H2L_F1 <= Pin_In;
   H2L_F2 <= H2L_F1;
   L2H_F1 <= Pin_In;
   L2H_F2 <= L2H_F1;
end

/***********************************/


   assign H2L_Sig = isEn ? ( H2L_F2 & !H2L_F1 ) : 1'b0;
   assign L2H_Sig = isEn ? ( !L2H_F2 & L2H_F1 ) : 1'b0;


   /***********************************/

endmodule



module delay_module
(
CLK, RSTn, H2L_Sig, L2H_Sig, Pin_Out
);

input CLK;
   input RSTn;
   input H2L_Sig;
   input L2H_Sig;
   output Pin_Out;

   /****************************************/

   parameter T1MS = 16'd19_999;

   /***************************************/

   reg [15:0]Count1;

   always @ ( posedge CLK or negedge RSTn )
      if( !RSTn )
      Count1 <= 16'd0;
   else if( isCount && Count1 == T1MS )
      Count1 <= 16'd0;
   else if( isCount )
      Count1 <= Count1 + 1'b1;
   else if( !isCount )
      Count1 <= 16'd0;

/****************************************/

reg [3:0]Count_MS;

   always @ ( posedge CLK or negedge RSTn )
      if( !RSTn )
      Count_MS <= 4'd0;
   else if( isCount && Count1 == T1MS )
      Count_MS <= Count_MS + 1'b1;
   else if( !isCount )
      Count_MS <= 4'd0;

/******************************************/

reg isCount;
reg rPin_Out;
reg [1:0]i;

always @ ( posedge CLK or negedge RSTn )
      if( !RSTn )
      begin
         isCount <= 1'b0;
rPin_Out <= 1'b0;
i <= 2'd0;
   end
   else
      case ( i )

      2'd0 :
   if( H2L_Sig ) i <= 2'd1;
   else if( L2H_Sig ) i <= 2'd2;

      2'd1 :
   if( Count_MS == 4'd10 ) begin isCount <= 1'b0; rPin_Out <= 1'b1; i <= 2'd0; end
      else isCount <= 1'b1;

   2'd2 :
   if( Count_MS == 4'd10 ) begin isCount <= 1'b0; rPin_Out <= 1'b0; i <= 2'd0; end
      else isCount <= 1'b1;


endcase

/********************************************/

   assign Pin_Out = rPin_Out;

   /********************************************/


endmodule

检测按键,延时消抖,程序思路跟C很像,容易理解