SP605调试SFP代码，在MAP时过到ERROR:Place:1111-第2页回答

SP605调试SFP代码，在MAP时过到ERROR:Place:1111

2020-02-23 10:47发布

本帖最后由 fencanyy 于 2012-12-27 10:25 编辑

我的SFP测试代码修改自官方的sp605_BRD_rdf0033_13.3_c.zip，SP605_BRD/SP605_BRD_Src/Logic/
下载地址：
secure.xilinx.com/webreg/clickthrough.do?cid=176876&license=RefDesLicense&filename=sp605_BRD_rdf0033_13.3_c.zip
原来自带的代码中有对GTP收-发数据检验测试的，它测的是SMA接口，代码编译下装测试都OK的。
我修改了下代码准备测试SFP接口。
修改如下：
1、修改SP605_BRD.ucf文件
NET "RXN_IN"                   LOC = "C9";
NET "RXP_IN"                   LOC = "D9";
NET "TXN_OUT"                   LOC = "A8";
NET "TXP_OUT"                   LOC = "B8";
改成
NET "RXN_IN"                   LOC = "C13";
NET "RXP_IN"                   LOC = "D13";
NET "TXN_OUT"                   LOC = "A14";
NET "TXP_OUT"                   LOC = "B14";

INST gtp_lpbk/s6_gtpwizard_v1_3_i/tile0_s6_gtpwizard_v1_3_i/gtpa1_dual_i LOC=GTPA1_DUAL_X0Y0;
改成
INST gtp_lpbk/s6_gtpwizard_v1_3_i/tile0_s6_gtpwizard_v1_3_i/gtpa1_dual_i LOC=GTPA1_DUAL_X1Y0;

2、修改s6_gtpwizard_v1_3_top.v文件
.TILE0_RXN1_IN                (RXN_IN),
.TILE0_RXP1_IN                (RXP_IN),
.TILE0_TXN1_IN                (TXN_IN),
.TILE0_TXP1_IN                (TXP_IN),
改为
.TILE0_RXN0_IN                (RXN_IN),
.TILE0_RXP0_IN                (RXP_IN),
.TILE0_TXN0_IN                (TXN_IN),
.TILE0_TXP0_IN                (TXP_IN),

assign track_data_out_i = tile0_track_data1_i ;
改为
assign track_data_out_i = tile0_track_data0_i ;

然后Synthesize成功，Translate成功，在Map时出现如下错误：
ERROR:Place:1111 - Unroutable Placement! A BUFIO / BUFGMUX clock component pair
have been found that are not placed at a routable BUFIO / BUFGMUX site pair.
The BUFIO component <gtp_lpbk/gtpclkout0_0_bufg0_bufio2_i> is placed at site
<BUFIO2_X4Y28>. The BUFGMUX component <gtp_lpbk/gtpclkout0_0_bufg0_i> is
placed at site <BUFGMUX_X2Y9>. Each BUFGMUX site has a select set of BUFIOs
that can drive it. If these BUFIOs are not used, the connection is not
routable You may want to analyze why this problem exists and correct it. This
placement is UNROUTABLE in PAR and therefore, this error condition should be
fixed in your design. You may use the CLOCK_DEDICATED_ROUTE constraint in the
.ucf file to demote this message to a WARNING in order to generate an NCD
file. This NCD file can then be used in FPGA Editor to debug the problem. A
list of all the COMP.PINS used in this clock placement rule is listed below.
These examples can be used directly in the .ucf file to demote this ERROR to
a WARNING.
< PIN "gtp_lpbk/gtpclkout0_0_bufg0_bufio2_i.DIVCLK" CLOCK_DEDICATED_ROUTE =
FALSE; >
看意思好像是说<BUFIO2_X4Y28>与<BUFGMUX_X2Y9>位置有冲突，这个如何解决啊？

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