麻烦请教个问题，我在map时报出了这个错误ERROR PhysDesignRules:1461 - Incomplete PLL_ADV configuration. The signal
system_i/clock_generator_0/clock_generator_0/SIG_PLL0_CLKFBOUT on the CLKFBIN
pin of PLL_ADV comp
system_i/clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_
inst is driven by the PLL_ADV CLKFBOUT pin therefore the COMPENSATION
attribute must be set INTERNAL, DCM2PLL, or PLL2DCM.
ERROR Pack:1642 - Errors in physical DRC.
不知道这个该如何解决？难得要修改*.MHS文件里面的CLK的属性？
我现在是把PLL模块产生的时钟信号输出到ISE中作为逻辑模块的时钟信号MHS的语句为
PORT sysclk = clk_66_6667MHz, DIR = O, SIGIS = CLK, CLK_FREQ = 66666666
友情提示: 此问题已得到解决，问题已经关闭,关闭后问题禁止继续编辑，回答。
{var%20f='http://v.t.sina.com.cn/share/share.php?appkey=1515056452',u=z||d.location,p=['&url=',e(u),'&title=',e(t||d.title),'&source=',e(r),'&sourceUrl=',e(l),'&content=',c||'gb2312','&pic=',e(p||'')].join('');function%20a(){if(!window.open([f,p].join(''),'mb',['toolbar=0,status=0,resizable=1,width=440,height=430,left=',(s.width-440)/2,',top=',(s.height-430)/2].join('')))u.href=[f,p].join('');};if(/Firefox/.test(navigator.userAgent))setTimeout(a,0);else%20a();})(screen,document,encodeURIComponent,'','','https://www.xiaopingtou.cn/data/attach/logo/logo.png', '推荐 520810 的问题《Map时报出 的错误》','https://www.xiaopingtou.net/q-175988.html','页面编码gb2312|utf-8默认gb2312'));){kind=link}
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