输入的数据带同步时钟,频率74.25,用dcm得到2倍频i_gv7601_clk_2X1,2倍频频率148.5m。
reg[15:0] gv7601_data1;
always@(negedge i_gv7601_clk_2X1)
begin
gv7601_data1 <= i_gv7601_data1;
end
//--------------------------------------
// GV7601 Data Output
//--------------------------------------
always@(posedge i_gv7601_clk_2X1,negedge i_gv7601_rstn1)
begin
if(~i_gv7601_rstn1)
o_BT1120_data1 <= 0;
else
o_BT1120_data1 <= gv7601_data1;
end
clk=74.25m,clk2X=148.5m,绝大部分数据都是错误的
reg[15:0] gv7601_data1;
always@(negedge i_gv7601_clk_2X1)
begin
gv7601_data1 <= i_gv7601_data1;
end
//--------------------------------------
// GV7601 Data Output
//--------------------------------------
always@(posedge i_gv7601_clk_2X1,negedge i_gv7601_rstn1)
begin
if(~i_gv7601_rstn1)
o_BT1120_data1 <= 0;
else
o_BT1120_data1 <= gv7601_data1;
end
o_BT1120_data1 输出给后面的模块使用
dcm的output clk_2x相位同步了么,同步的话至少每隔一次是对的
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