本帖最后由 aceice 于 2013-6-21 10:59 编辑

clk信号输入到FPGA，一路提供给DCM的clkin，一路提供给另外一部分逻辑。
直接综合的话，会提示：
ERROR:Xst:2035 - Port <clk_50MHz> has illegal connections. This port is connected to an input buffer and other components.

在综合选项里将Add I/O Buffers取消，可以综合过去，但是Translate又会提示错误：
ERROR:NgdBuild:924 - input pad net 'clk_50MHz' is driving non-buffer primitives:

按照网上一份资料，说的是生成的DCM，包含一个IBUFG，遂手工将DCM源码里的IBUFG去掉。
再次Translate，提示一个警告
WARNING:ConstraintSystem:119 - Constraint <NET "clk_50MHz" LOC = A8;>
   [TestIBUFG.ucf(3)]: This constraint cannot be distributed from the design
   objects matching 'NET "clk_50MHz"' because those design objects do not
   contain or drive any instances of the correct type.
并且Map出错，提示
ERROR:Pack:198 - NCD was not produced.  All logic was removed from the design.
   This is usually due to having no input or output PAD connections in the
   design and no nets or symbols marked as 'SAVE'.  You can either add PADs or
   'SAVE' attributes to the design, or run 'map -u' to disable logic trimming in
   the mapper.  For more information on trimming issues search the Xilinx

再次将Add I/O Buffers勾选上，Translate，Map都没问题，但是Place & Route会有个警告：
WARNING:Route:455 - CLK Net:clk_50MHz_IBUFG may have excessive skew because
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怎么解决这个问题？