还有在 mig_7series_v1_7_s7ven_data_gen里面 parameter nCK_PER_CLK = 2，是不是程序错了，这个参数不是应该是4 吗？
还有generate
if (nCK_PER_CLK == 2)
begin: calib_data32
always @ (posedge clk_i)
if (rst_i) begin
    next_calib_data <= 1'b0;
    calib_data <=  #TCQ {{(NUM_DQ_PINS/8){8'h55}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h00}},{(NUM_DQ_PINS/8){8'hff}}};
    end   
else if (cmd_startA)
     begin
     calib_data <=  #TCQ {{(NUM_DQ_PINS/8){8'h55}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h00}},{(NUM_DQ_PINS/8){8'hff}}};
     next_calib_data <=#TCQ  1'b1;
//     calib_data <= 'b0;
     end
   else if (fifo_rdy_i)  
     begin
     next_calib_data <= #TCQ  ~next_calib_data;
     if (next_calib_data )
     
     calib_data <= #TCQ  {{(NUM_DQ_PINS/8){8'h66}},{(NUM_DQ_PINS/8){8'h99}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h55}}};
     else
     calib_data <= #TCQ  {{(NUM_DQ_PINS/8){8'h55}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h00}},{(NUM_DQ_PINS/8){8'hff}}};
     end
end
else
begin: calib_data64  // when nCK_PER_LK =4 has not verified
always @ (posedge clk_i)

if (rst_i) begin
    next_calib_data <= 1'b0;
    calib_data <=  #TCQ {{(NUM_DQ_PINS/8){16'h5555}},{(NUM_DQ_PINS/8){16'haaaa}},{(NUM_DQ_PINS/8){16'h0000}},{(NUM_DQ_PINS/8){16'hffff}}};
    end   
else if (cmd_startA)
   begin
     calib_data <=  #TCQ {{(NUM_DQ_PINS/8){16'h5555}},{(NUM_DQ_PINS/8){16'haaaa}},{(NUM_DQ_PINS/8){16'h0000}},{(NUM_DQ_PINS/8){16'hffff}}};
     next_calib_data <=#TCQ  1'b1;
//     calib_data <= 'b0;
     end
   else if (fifo_rdy_i)  
     begin
     next_calib_data <= #TCQ  ~next_calib_data;
     if (next_calib_data )
     
     calib_data <= #TCQ  {{(NUM_DQ_PINS/8){16'h6666}},{(NUM_DQ_PINS/8){16'h9999}},{(NUM_DQ_PINS/8){16'haaaa}},{(NUM_DQ_PINS/8){16'h5555}}};
     else
     calib_data <= #TCQ  {{(NUM_DQ_PINS/8){16'h5555}},{(NUM_DQ_PINS/8){16'haaaa}},{(NUM_DQ_PINS/8){16'h0000}},{(NUM_DQ_PINS/8){16'hffff}}};
     end


end
endgenerate

这段应该是PHY校验的数据吧，为什么我把这一段删掉里了，似乎对校验过程没有影响。