我有两个问题想问题一下
第一个问题：为什么我在下载程序的时候，蜂鸣器会一直响？
第二个问题:我按照特权同学的分频器教程写了如下程序：
module div_beep(clk,rst_n,fm);

input clk;//50MHZ
input rst_n;//低电平复位
output fm;//蜂鸣器 0--响 1--不响

/*reg[23:0] cnt; //分频计数器 1M分频


always @ (posedge clk or negedge rst_n )//异步复位
        if(!rst_n) cnt <=20'd0;
        else cnt <= cnt+1'b1;

assign fm = cnt[23];*/

assign fm = 1'b0;

       
endmodule
发现下载没有效果。程序有以下warning
Warning: Output pins are stuck at VCC or GND
        Warning (13410): Pin "fm" is stuck at GND
Warning: Design contains 2 input pin(s) that do not drive logic
        Warning (15610): No output dependent on input pin "clk"
        Warning (15610): No output dependent on input pin "rst_n"
Warning: No clocks defined in design.
Warning: No clocks defined in design.
Warning: No clocks defined in design.
Warning: An incorrect timescale is selected for the Verilog Output (.VO) file of this PLL design. It's required that the timescale should be 1 ps when simulating a PLL design in a third party EDA tool.
Warning: Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER