//---------------------STYLE #2-------------------------

module fifo2 (rdata, wfull, rempty, wdata,

winc, wclk, wrst_n, rinc, rclk, rrst_n);

parameter DSIZE = 8;

parameter ASIZE = 4;

output [DSIZE-1:0] rdata;

output wfull;

output rempty;

input [DSIZE-1:0] wdata;

input winc, wclk, wrst_n;

input rinc, rclk, rrst_n;

wire [ASIZE-1:0] wptr, rptr;

wire [ASIZE-1:0] waddr, raddr;

async_cmp #(ASIZE) async_cmp(.aempty_n(aempty_n),

.afull_n(afull_n),

.wptr(wptr), .rptr(rptr),

.wrst_n(wrst_n));

fifomem2 #(DSIZE, ASIZE) fifomem2(.rdata(rdata),

.wdata(wdata),

.waddr(wptr),

.raddr(rptr),

.wclken(winc),

.wclk(wclk));

rptr_empty2 #(ASIZE) rptr_empty2(.rempty(rempty),

.rptr(rptr),

.aempty_n(aempty_n),

.rinc(rinc),

.rclk(rclk),

.rrst_n(rrst_n));

wptr_full2 #(ASIZE) wptr_full2(.wfull(wfull),

.wptr(wptr),

.afull_n(afull_n),

.winc(winc),

.wclk(wclk),

.wrst_n(wrst_n));

endmodule

module fifomem2 (rdata, wdata, waddr, raddr, wclken, wclk);

parameter DATASIZE = 8; // Memory data word width

parameter ADDRSIZE = 4; // Number of memory address bits

parameter DEPTH = 1<<ADDRSIZE; // DEPTH = 2**ADDRSIZE

output [DATASIZE-1:0] rdata;

input [DATASIZE-1:0] wdata;

input [ADDRSIZE-1:0] waddr, raddr;

input wclken, wclk;

`ifdef VENDORRAM

// instantiation of a vendor's dual-port RAM

VENDOR_RAM MEM (.dout(rdata), .din(wdata),

.waddr(waddr), .raddr(raddr),

.wclken(wclken), .clk(wclk));

`else

reg [DATASIZE-1:0] MEM [0: DEPTH-1];

assign rdata = MEM[raddr];

always @(posedge wclk)

if (wclken) MEM[waddr] <= wdata;

`endif

endmodule

module async_cmp (aempty_n, afull_n, wptr, rptr, wrst_n);

parameter ADDRSIZE = 4;

parameter N = ADDRSIZE-1;

output aempty_n, afull_n;

input [N:0] wptr, rptr;

input wrst_n;

reg direction;

wire high = 1'b1;

wire dirset_n = ~( (wptr[N]^rptr[N-1]) & ~(wptr[N-1]^rptr[N]));

wire dirclr_n = ~((~(wptr[N]^rptr[N-1]) & (wptr[N-1]^rptr[N])) |

~wrst_n);

always @(posedge high or negedge dirset_n or negedge dirclr_n)

if (!dirclr_n) direction <= 1'b0;

else if (!dirset_n) direction <= 1'b1;

else direction <= high;

//always @(negedge dirset_n or negedge dirclr_n)

//if (!dirclr_n) direction <= 1'b0;

//else direction <= 1'b1;

assign aempty_n = ~((wptr == rptr) && !direction);

assign afull_n = ~((wptr == rptr) && direction);

endmodule

module rptr_empty2 (rempty, rptr, aempty_n, rinc, rclk, rrst_n);

parameter ADDRSIZE = 4;

output rempty;

output [ADDRSIZE-1:0] rptr;

input aempty_n;

input rinc, rclk, rrst_n;

reg [ADDRSIZE-1:0] rptr, rbin;

reg rempty, rempty2;

wire [ADDRSIZE-1:0] rgnext, rbnext;

//---------------------------------------------------------------

// GRAYSTYLE2 pointer

//---------------------------------------------------------------

always @(posedge rclk or negedge rrst_n)

if (!rrst_n) begin

rbin <= 0;

rptr <= 0;

end

else begin

rbin <= rbnext;

rptr <= rgnext;

end

//---------------------------------------------------------------

// increment the binary count if not empty

//---------------------------------------------------------------

assign rbnext = !rempty ? rbin + rinc : rbin;

assign rgnext = (rbnext>>1) ^ rbnext; // binary-to-gray conversion

always @(posedge rclk or negedge aempty_n)

if (!aempty_n) {rempty,rempty2} <= 2'b11;

else {rempty,rempty2} <= {rempty2,~aempty_n};

endmodule

module wptr_full2 (wfull, wptr, afull_n, winc, wclk, wrst_n);

parameter ADDRSIZE = 4;

output wfull;

output [ADDRSIZE-1:0] wptr;

input afull_n;

input winc, wclk, wrst_n;

reg [ADDRSIZE-1:0] wptr, wbin;

reg wfull, wfull2;

wire [ADDRSIZE-1:0] wgnext, wbnext;

//---------------------------------------------------------------

// GRAYSTYLE2 pointer

//---------------------------------------------------------------

always @(posedge wclk or negedge wrst_n)

if (!wrst_n) begin

wbin <= 0;

wptr <= 0;

end

else begin

wbin <= wbnext;

wptr <= wgnext;

end

//---------------------------------------------------------------

// increment the binary count if not full

//---------------------------------------------------------------

assign wbnext = !wfull ? wbin + winc : wbin;

assign wgnext = (wbnext>>1) ^ wbnext; // binary-to-gray conversion

always @(posedge wclk or negedge wrst_n or negedge afull_n)

if (!wrst_n ) {wfull,wfull2} <= 2'b00;

else if (!afull_n) {wfull,wfull2} <= 2'b11;

else {wfull,wfull2} <= {wfull2,~afull_n};

endmodule

缁嗗績鐨勮鑰呬細鍙戠幇锛岀涓€绉嶅啓娉曪紙鏈汉鍋氱殑淇敼锛夋妸鎵€鏈変俊鍙峰啓鍦ㄥ悓涓€涓猰odule閲岋紝鑰岀浜岀鍐欐硶鍒欏垎浜嗗緢澶氭ā鍧椼€傚摢绉嶅啓娉曟洿濂藉憿锛熸湁鍏磋叮鐨勫彲浠ユ兂涓€鎯筹紝浜嬪疄涓婏紝绗簩绉嶅啓娉曟槸鎺ㄨ崘鐨勫啓娉曪細鍘熷洜濡備笅锛?/font>

寮傛鐨勫鏃堕挓璁捐搴旀寜浠ヤ笅鍑犱釜鍘熷垯杩涜璁捐锛?/font>

1锛屽敖鍙兘鐨勫皢澶氭椂閽熺殑閫昏緫鐢佃矾锛堥潪鍚屾鍣級鍒嗗壊涓哄涓崟鏃堕挓鐨勬ā鍧楋紝杩欐牱鏈夊埄浜庨潤鎬佹椂搴忓垎鏋愬伐鍏锋潵杩涜鏃跺簭楠岃瘉銆?/font>

2锛屽悓姝ュ櫒鐨勫疄鐜板簲浣垮緱鎵€鏈夎緭鍏ユ潵鑷悓涓€涓椂閽熷煙锛岃€屼娇鐢ㄥ彟涓€涓椂閽熷煙鐨勫紓姝ユ椂閽熶俊鍙烽噰鏍锋暟鎹€?/font>

3锛岄潰鍚戞椂閽熶俊鍙风殑鍛藉悕鏂瑰紡鍙互甯姪鎴戜滑纭畾閭ｄ簺鍦ㄤ笉鍚屽紓姝ユ椂閽熷煙闂撮渶瑕佸鐞嗙殑淇″彿銆?/font>

4锛屽綋瀛樺湪澶氫釜璺ㄦ椂閽熷煙鐨勬帶鍒朵俊鍙锋椂锛屾垜浠繀椤荤壒鍒敞鎰忚繖浜涗俊鍙凤紝淇濊瘉杩欎簺鎺у埗淇″彿鍒拌揪鏂扮殑鏃堕挓鍩熶粛鐒惰兘澶熶繚鎸佹纭殑椤哄簭銆?/font>