本帖最后由 ldcxsp 于 2013-6-28 16:58 编辑

配置完MPMC, 经chipscope采样 MPMC_Init_DONE 为高， 但在XILINX EDK 中 内存选择MPMC 时程序不能运行，
下面是MHS 文件， 求解决?
一旦sdk 跑程序 MPMC_Init_DONE 又会被拉低。
# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 14.4 Build EDK_P.49d
# Wed Jun 26 10:31:36 2013
# Target Board:  Custom
# Family:    spartan6
# Device:    xc6slx100t
# Package:   fgg676
# Speed Grade:  -3
# Processor number: 1
# Processor 1: microblaze_0
# System clock frequency: 66.7
# Debug Interface: On-Chip HW Debug Module
# ##############################################################################
PARAMETER VERSION = 2.1.0

PORT fpga_0_clk_1_sys_clk_pin = CLK_S, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
PORT mpmc_0_mcbx_dram_addr_pin = mpmc_0_mcbx_dram_addr, DIR = O, VEC = [12:0]
PORT mpmc_0_mcbx_dram_ba_pin = mpmc_0_mcbx_dram_ba, DIR = O, VEC = [2:0]
PORT mpmc_0_mcbx_dram_ras_n_pin = mpmc_0_mcbx_dram_ras_n, DIR = O
PORT mpmc_0_mcbx_dram_cas_n_pin = mpmc_0_mcbx_dram_cas_n, DIR = O
PORT mpmc_0_mcbx_dram_we_n_pin = mpmc_0_mcbx_dram_we_n, DIR = O
PORT mpmc_0_mcbx_dram_cke_pin = mpmc_0_mcbx_dram_cke, DIR = O
PORT mpmc_0_mcbx_dram_clk_pin = mpmc_0_mcbx_dram_clk, DIR = O, SIGIS = CLK
PORT mpmc_0_mcbx_dram_clk_n_pin = mpmc_0_mcbx_dram_clk_n, DIR = O, SIGIS = CLK
PORT mpmc_0_mcbx_dram_dq = mpmc_0_mcbx_dram_dq, DIR = IO, VEC = [15:0]
PORT mpmc_0_mcbx_dram_dqs = mpmc_0_mcbx_dram_dqs, DIR = IO
PORT mpmc_0_mcbx_dram_dqs_n = mpmc_0_mcbx_dram_dqs_n, DIR = IO
PORT mpmc_0_mcbx_dram_udqs = mpmc_0_mcbx_dram_udqs, DIR = IO
PORT mpmc_0_mcbx_dram_udqs_n = mpmc_0_mcbx_dram_udqs_n, DIR = IO
PORT mpmc_0_mcbx_dram_udm_pin = mpmc_0_mcbx_dram_udm, DIR = O
PORT mpmc_0_mcbx_dram_ldm_pin = mpmc_0_mcbx_dram_ldm, DIR = O
PORT mpmc_0_mcbx_dram_odt_pin = mpmc_0_mcbx_dram_odt, DIR = O
PORT mpmc_0_mcbx_dram_ddr3_rst_pin = mpmc_0_mcbx_dram_ddr3_rst, DIR = O
PORT mpmc_0_MPMC_InitDone_pin = mpmc_0_MPMC_InitDone, DIR = O
PORT mpmc_0_rzq = mpmc_0_rzq, DIR = IO
PORT mpmc_0_zio = mpmc_0_zio, DIR = IO

BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER C_USE_BARREL = 1
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER HW_VER = 8.40.b
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DPLB = mb_plb
BUS_INTERFACE IPLB = mb_plb
BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
PORT MB_RESET = mb_reset
END
BEGIN plb_v46
PARAMETER INSTANCE = mb_plb
PARAMETER HW_VER = 1.05.a
PORT SYS_Rst = sys_bus_reset
PORT PLB_Clk = clock_generator_0_CLKOUT1
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 2.00.b
PORT SYS_Rst = sys_bus_reset
PORT LMB_Clk = clock_generator_0_CLKOUT1
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 2.00.b
PORT SYS_Rst = sys_bus_reset
PORT LMB_Clk = clock_generator_0_CLKOUT1
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 3.10.c
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 3.10.c
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER C_CLKIN_FREQ = 50000000
PARAMETER C_CLKOUT0_FREQ = 333333333
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = NONE
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER C_EXT_RESET_HIGH = 1
PARAMETER HW_VER = 4.03.a
PARAMETER C_CLKOUT1_FREQ = 100000000
PARAMETER C_CLKOUT2_FREQ = 100000000
PARAMETER C_CLKOUT1_GROUP = PLL0
PARAMETER C_CLKOUT1_BUF = TRUE
PARAMETER C_CLKOUT2_PHASE = 0
PARAMETER C_CLKOUT2_GROUP = PLL0
PARAMETER C_CLKOUT2_BUF = TRUE
PARAMETER C_CLKOUT3_FREQ = 0
PARAMETER C_CLKOUT3_GROUP = PLL1
PARAMETER C_CLKOUT1_PHASE = 0
PORT CLKIN = CLK_S
PORT CLKOUT0 = clk_66_6667MHz
PORT RST = sys_rst_s
PORT LOCKED = Dcm_all_locked
PORT CLKOUT1 = clock_generator_0_CLKOUT1
PORT CLKOUT2 = clock_generator_0_CLKOUT2
END
BEGIN mdm
PARAMETER INSTANCE = mdm_0
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER HW_VER = 2.10.a
PARAMETER C_BASEADDR = 0x84400000
PARAMETER C_HIGHADDR = 0x8440ffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus
PORT Debug_SYS_Rst = Debug_SYS_Rst
END
BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER C_EXT_RESET_HIGH = 1
PARAMETER HW_VER = 3.00.a
PORT Slowest_sync_clk = clock_generator_0_CLKOUT1
PORT Ext_Reset_In = sys_rst_s
PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
PORT Dcm_locked = Dcm_all_locked
PORT MB_Reset = mb_reset
PORT Bus_Struct_Reset = sys_bus_reset
PORT Peripheral_Reset = sys_periph_reset
END
BEGIN mpmc
PARAMETER INSTANCE = mpmc_0
PARAMETER HW_VER = 6.06.a
PARAMETER C_PORT_CONFIG = 1
PARAMETER C_MCB_LOC = MEMC3
PARAMETER C_PIM1_BASETYPE = 6
PARAMETER C_PIM2_BASETYPE = 6
PARAMETER C_PIM3_BASETYPE = 6
PARAMETER C_MEM_PARTNO = MT41J64M16XX-15E
PARAMETER C_MEM_TYPE = DDR3
PARAMETER C_MEM_DATA_WIDTH = 16
PARAMETER C_MEM_ODT_TYPE = 1
PARAMETER C_VFBC1_RDWD_FIFO_DEPTH = 2048
PARAMETER C_VFBC2_RDWD_FIFO_DEPTH = 2048
PARAMETER C_VFBC3_RDWD_DATA_WIDTH = 64
PARAMETER C_VFBC3_RDWD_FIFO_DEPTH = 2048
PARAMETER C_NUM_PORTS = 4
PARAMETER C_MCB_ZIO_LOC = AA4
PARAMETER C_MCB_RZQ_LOC = AB5
PARAMETER C_MEM_CALIBRATION_SOFT_IP = TRUE
PARAMETER C_MEM_SKIP_IN_TERM_CAL = 0
PARAMETER C_MEM_SKIP_DYN_IN_TERM = 1
PARAMETER C_MEM_SKIP_DYNAMIC_CAL = 0
PARAMETER C_MPMC_BASEADDR = 0x88000000
PARAMETER C_MPMC_HIGHADDR = 0x8FFFFFFF
BUS_INTERFACE SPLB0 = mb_plb
PORT MPMC_Rst = sys_bus_reset
PORT mcbx_dram_addr = mpmc_0_mcbx_dram_addr
PORT mcbx_dram_ba = mpmc_0_mcbx_dram_ba
PORT mcbx_dram_ras_n = mpmc_0_mcbx_dram_ras_n
PORT mcbx_dram_cas_n = mpmc_0_mcbx_dram_cas_n
PORT mcbx_dram_we_n = mpmc_0_mcbx_dram_we_n
PORT mcbx_dram_cke = mpmc_0_mcbx_dram_cke
PORT mcbx_dram_clk = mpmc_0_mcbx_dram_clk
PORT mcbx_dram_clk_n = mpmc_0_mcbx_dram_clk_n
PORT mcbx_dram_dq = mpmc_0_mcbx_dram_dq
PORT mcbx_dram_dqs = mpmc_0_mcbx_dram_dqs
PORT mcbx_dram_dqs_n = mpmc_0_mcbx_dram_dqs_n
PORT mcbx_dram_udqs = mpmc_0_mcbx_dram_udqs
PORT mcbx_dram_udqs_n = mpmc_0_mcbx_dram_udqs_n
PORT mcbx_dram_udm = mpmc_0_mcbx_dram_udm
PORT mcbx_dram_ldm = mpmc_0_mcbx_dram_ldm
PORT mcbx_dram_odt = mpmc_0_mcbx_dram_odt
PORT mcbx_dram_ddr3_rst = mpmc_0_mcbx_dram_ddr3_rst
PORT rzq = mpmc_0_rzq
PORT zio = mpmc_0_zio
PORT MPMC_Clk_Mem_2x = pll_module_0_CLKOUT0
PORT MPMC_Clk_Mem_2x_180 = pll_module_0_CLKOUT1
PORT MPMC_PLL_Lock = pll_module_0_LOCKED
PORT MPMC_MCB_DRP_Clk = pll_module_0_CLKOUT2
PORT MPMC_Clk0 = clock_generator_0_CLKOUT2
PORT MPMC_InitDone = mpmc_0_MPMC_InitDone
END
BEGIN pll_module
PARAMETER INSTANCE = pll_module_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_CLKFBOUT_MULT = 2
PARAMETER C_CLKIN1_PERIOD = 3.0
PARAMETER C_CLKOUT1_PHASE = 180.000000
PARAMETER C_CLKOUT2_DIVIDE = 8
PARAMETER C_REF_JITTER = 0.00500000
PARAMETER C_CLKOUT2_BUF = true
PARAMETER C_CLKOUT1_DIVIDE = 1
PARAMETER C_COMPENSATION = INTERNAL
PARAMETER C_CLKFBOUT_BUF = false
PORT CLKOUT0 = pll_module_0_CLKOUT0
PORT CLKOUT1 = pll_module_0_CLKOUT1
PORT CLKOUT2 = pll_module_0_CLKOUT2
PORT CLKFBOUT = pll_module_0_CLKFBOUT
PORT CLKFBIN = pll_module_0_CLKFBOUT
PORT CLKIN1 = clk_66_6667MHz
PORT RST = sys_rst_s
PORT LOCKED = pll_module_0_LOCKED
END