void UART_IRQHandler(void)
{
uint8_t IIRValue, LSRValue;
uint8_t Dummy = Dummy;
IIRValue = LPC_USART->IIR;
IIRValue >>= 1;
IIRValue &= 0x07;
if (IIRValue == IIR_RLS)
{
LSRValue = LPC_USART->LSR;
/* Receive Line Status */
if (LSRValue & (LSR_OE | LSR_PE | LSR_FE | LSR_RXFE | LSR_BI))
{
UARTStatus = LSRValue;
Dummy = LPC_USART->RBR; /* Dummy read on RX to clear
interrupt, then bail out */
return;
}
if (LSRValue & LSR_RDR) /* Receive Data Ready */
{
UARTBuffer[UARTCount++] = LPC_USART->RBR;
if (UARTCount == BUFSIZE)
{
UARTCount = 0; }
}
}
else if (IIRValue == IIR_RDA) {
UARTBuffer[UARTCount++] = LPC_USART->RBR;
if (UARTCount == BUFSIZE)
{
UARTCount = 0; /* buffer overflow */
}
}
else if (IIRValue == IIR_CTI) /* Character timeout indicator */
{
UARTStatus |= 0x100; /* Bit 9 as the CTI error */
}
else if (IIRValue == IIR_THRE)
{
/* THRE interrupt */
LSRValue = LPC_USART->LSR; /* Check status in the LSR to see if
valid data in U0THR or not */
if (LSRValue & LSR_THRE)
{
UARTTxEmpty = 1;
}
else
{
UARTTxEmpty = 0;
}
}
return;
}
void UARTInit(uint32_t baudrate)
{
uint32_t Fdiv;
uint32_t regVal;
UARTTxEmpty = 1;
UARTCount = 0;
NVIC_DisableIRQ(UART_IRQn);
#if
LPC_IOCON->PIO0_18 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO0_18 |= 0x01; /* UART RXD */
LPC_IOCON->PIO0_19 &= ~0x07;
LPC_IOCON->PIO0_19 |= 0x01; /* UART TXD */
#endif
#if 0
LPC_IOCON->PIO1_14 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_14 |= 0x03; /* UART RXD */
LPC_IOCON->PIO1_13 &= ~0x07;
LPC_IOCON->PIO1_13 |= 0x03; /* UART TXD */
#endif
#if 0
LPC_IOCON->PIO1_17 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_17 |= 0x02; /* UART RXD */
LPC_IOCON->PIO1_18 &= ~0x07;
LPC_IOCON->PIO1_18 |= 0x02; /* UART TXD */
#endif
#if 0
LPC_IOCON->PIO1_26 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_26 |= 0x02; /* UART RXD */
LPC_IOCON->PIO1_27 &= ~0x07;
LPC_IOCON->PIO1_27 |= 0x02; /* UART TXD */
#endif
/* Enable UART clock */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
LPC_SYSCON->UARTCLKDIV = 0x1;
LPC_USART->LCR = 0x83;
regVal = LPC_SYSCON->UARTCLKDIV;
Fdiv = ((SystemCoreClock/regVal)/16)/baudrate ; /*baud rate */
LPC_USART->DLM = Fdiv / 256;
LPC_USART->DLL = Fdiv % 256;
LPC_USART->LCR = 0x03;
LPC_USART->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
/* Read to clear the line status. */
regVal = LPC_USART->LSR;
while (( LPC_USART->LSR & (LSR_THRE|LSR_TEMT)) != (LSR_THRE|LSR_TEMT) );
while ( LPC_USART->LSR & LSR_RDR )
{
regVal = LPC_USART->RBR;
}
NVIC_EnableIRQ(UART_IRQn);
#if TX_INTERRUPT
LPC_USART->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART interrupt */
#else
LPC_USART->IER = IER_RBR | IER_RLS; /* Enable UART interrupt */
#endif
return;
}
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