OMAP5432的MPU_DPLL应该如何配置，手册中这样描述的The DPLL can be programmed to be locked at any frequency given by one of the following equations:
• Fdpll = Fref × 2 × M / (N + 1)
• Fdpll = Fref × 2 × (4 × M / (N + 1)) in case the CM_CLKMODE_DPLL_ABE[11] DPLL_REGM4XEN bit is
set (applies only to DPLL_ABE)
• Fdpll = Fref × (M / (N + 1)) in case the CM_CLKSEL_DPLL_MPU[22] DCC_EN bit is set (applies only to
DPLL_MPU when frequency higher than 1.4GHz is needed).
我需要配置1100MHZ的MPU_DPLL应该如何设置？是使用Fdpll = Fref * 2 * M/(N+1)还是Fdpll = Fref * (M/(N+1))呢？
OMAP5432 EVM板载uboot中是这样配置的{1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},按上面的式子算出来是2200MHZ，请问，为什么选用下面的式子？？由于板载uboot配置的MPU_DPLL输出为1100MHZ，没有超过1.4GHZ，应该不满足使用下面式子的条件吧，求高手指点 此帖出自小平头技术问答