求大家给一个msp430硬件spi操作nrf24l01的代码吧，自己写的老是发送失败

2019-03-24 08:57发布

站内问答 / TI MCU
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代码是移植的正点原子的，但是前面的spi配置部分是自己写的，大神帮忙看看哪里配置不对，硬件spi跟软件模拟spi都试过了
  1. void SPI3_Init()
  2. {
  3. #if HW_SPI
  4.   P10SEL|=BIT1+BIT2+BIT3;    //设置P10.1~P10.3外设功能
  5.   P10SEL&=~(BIT0+BIT4+BIT5);
  6.   P10DIR|=BIT0+BIT1+BIT3+BIT4;     //设置CS,MOSI,CLK,CE,为输出方向
  7.   P10DIR&=~(BIT2+BIT5);             //设置MISO为输入方向
  8.   P10DS|=BIT0+BIT1+BIT3+BIT4;     
  9.   P10REN|=BIT2+BIT5;              //设置MISO上拉
  10.   P10OUT|=BIT1+BIT2+BIT5;
  11.   P10OUT&=~BIT0+BIT3;
  12.   UCB3CTL1|=UCSWRST;      
  13.   UCB3CTL0 =UCCKPH+UCMSB+UCMST+UCMODE_0+UCSYNC;    //3线SPI主机模式，时钟极性低，先发送MSB
  14.   UCB3CTL0&=~(UCCKPL);
  15.   UCB3CTL1|=UCSSEL_2;          ///选择SMCLK
  16.   UCB3BR0=5;                  //25M/5=5M <10M
  17.   UCB3BR1=0;
  18.   UCB3CTL1&=~UCSWRST;
  19.   UCB3IE &= ~(UCRXIE+UCTXIE);  //不开中断
  20. //  UCB3IFG&=~UCRXIFG;
  21. #elif !HW_SPI
  22.   P10DIR|=BIT0+BIT1+BIT3+BIT4;  
  23.   P10DIR&=~(BIT2+BIT5);
  24.   P10DS|=BIT0+BIT1+BIT3+BIT4;     
  25.   P10REN|=BIT2+BIT5;           
  26.   P10OUT|=BIT2+BIT5;
  27.   P10OUT&=~BIT3;
  28. #endif
  29. }

  31. //连接方式
  32.     //P10.0->CSN    P10.1->MOSI
  33.     //P10.2->MISO   P10.3->CLK
  34.     //P10.4->CE     P10.5->IRQ

  36. u8 SPI3_SendReceiveByte(u8 byte)
  37. {
  38.   u8 val;
  39. #if HW_SPI
  40.   while (!(UCB3IFG&UCTXIFG));   //等待TXBUF为空
  41.   UCB3TXBUF=byte;
  42.   while((UCB3STAT&UCBUSY)&&(!(UCB3IFG&UCRXIFG)));    //等待发送跟接收完成
  43.   val=UCB3RXBUF;
  44. #elif !HW_SPI
  45.   u8 i;
  46.   for(i=0;i<8;i++)
  47.   {
  48.     if(byte&0x80)
  49.       NRFMOSI_1;
  50.     else
  51.       NRFMOSI_0;
  52.     byte<<=1;
  53.     NRFCLK_1;
  54.     if(NRFMISO)
  55.       byte|=0x01;
  56.     NRFCLK_0;
  57.   }
  58.   val=byte;
  59. #endif
  60.   return val;
  61.   
  62. }
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19条回答
jianping-sun
1楼-- · 2019-03-26 15:24
cjm1234 发表于 2016-6-26 22:57
楼主能贴下成功的代码嘛？感谢
  1. #include "NRF24L01.h"

  3. //P9.0 -> CE
  4. //P9.4 -> CSN
  5. //P9.5 -> IRQ


  8. uint8_t TX_ADDRESS[TX_ADR_WIDTH]={0x34,0x43,0x10,0x10,0x01}; //Send Addr
  9. uint8_t RX_ADDRESS[RX_ADR_WIDTH]={0x34,0x43,0x10,0x10,0x01}; //Receive Addr

  11. void NRF_GPIO_Config()  
  12. {
  13.   P9SEL &= ~(BIT0 + BIT4);
  14.   P9DIR |= BIT0 + BIT4;
  15.   P9DIR &= ~BIT5;
  16.   P9DS |= BIT0 + BIT4;
  17. }

  19. uint8_t NRF_WriteReg(uint8_t reg,uint8_t val)
  20. {
  21.   uint8_t temp = 0;
  22.   NRF_CSN_0;
  23.   temp = SPI2_SendReceive_SingleByte(reg);
  24.   SPI2_SendReceive_SingleByte(val);
  25.   NRF_CSN_1;
  26.   return temp;
  27. }

  29. uint8_t NRF_ReadReg(uint8_t reg)
  30. {
  31.   uint8_t val = 0;
  32.   NRF_CSN_0;
  33.   SPI2_SendReceive_SingleByte(reg);
  34.   val=SPI2_SendReceive_SingleByte(0xFF);
  35.   NRF_CSN_1;
  36.   return val;
  37. }

  39. uint8_t NRF_ReadBuf(uint8_t reg,uint8_t *buff,uint8_t num)
  40. {
  41.   uint8_t i = 0,val = 0;
  42.   NRF_CSN_0;
  43.   val = SPI2_SendReceive_SingleByte(reg);
  44.   for(i = 0;i < num;i++)
  45.     buff[i] = SPI2_SendReceive_SingleByte(0xFF);
  46.   NRF_CSN_1;
  47.   return val;
  48. }

  50. uint8_t NRF_WriteBuf(uint8_t reg,uint8_t *buff,uint8_t num)
  51. {
  52.   uint8_t val = 0,i = 0;
  53.   NRF_CSN_0;
  54.   val = SPI2_SendReceive_SingleByte(reg);
  55.   for(i = 0;i < num;i++)
  56.     SPI2_SendReceive_SingleByte(buff[i]);
  57.   NRF_CSN_1;
  58.   return val;
  59. }

  61. void Set_Rx_Mode()
  62. {
  63.   NRF_CE_0;
  64.   NRF_WriteReg(WRITE_REG+CONFIG, 0x0F);
  65.   NRF_CE_1;
  66.   delay_ms(1);
  67. }
  68. void Set_Tx_Mode()
  69. {
  70.   NRF_CE_0;
  71.   NRF_WriteReg(WRITE_REG+CONFIG, 0x0E);
  72.   NRF_CE_1;
  73.   delay_ms(1);
  74. }

  76. uint8_t NRF_SendPacket(uint8_t *TxBuf)
  77. {
  78.   uint8_t val = 0;
  79.   NRF_CE_0;
  80.   NRF_WriteBuf(WR_TX_PLOAD,TxBuf,TX_PLOAD_WIDTH);
  81.   Set_Tx_Mode();
  82.   NRF_CE_1;
  83.   delay_ms(1);
  84. //  while(NRF_IRQ != 0);
  85.   val=NRF_ReadReg(STATUS);
  86.   NRF_WriteReg(WRITE_REG+STATUS,0xFF);
  87.   if(val&TX_OK)
  88.     return TX_OK;
  89.   if(val&MAX_TX)
  90.   {
  91.     NRF_WriteReg(WRITE_REG+STATUS,0xff);
  92.     NRF_WriteReg(FLUSH_TX,0xFF);
  93.     return MAX_TX;
  94.   }
  95.   return 0xFF;
  96. }

  98. uint8_t NRF_ReceivePacket(uint8_t *RxBuf)
  99. {
  100.   uint8_t val = 0;
  101.   NRF_CE_0;
  102.   Set_Rx_Mode();
  103.   NRF_CE_1;
  104.   delay_us(500);
  105.   while(NRF_IRQ != 0);
  106.   val=NRF_ReadReg(STATUS);
  107.   if(val&RX_OK)
  108.   {
  109.     NRF_ReadBuf(RD_RX_PLOAD,RxBuf,RX_PLOAD_WIDTH);
  110.     NRF_WriteReg(FLUSH_RX,0xff);
  111.     return 0;
  112.   }
  113.   return 0xff;
  114. }

  116. void NRF_Config()
  117. {
  118.   delay_us(1000);
  119.   NRF_GPIO_Config();
  120.   SPI2_Init();
  121.   delay_us(250);
  122.   NRF_CE_0;
  123.   NRF_CSN_1;
  124.   P9OUT &= ~BIT3;
  125.   NRF_WriteBuf(WRITE_REG + TX_ADDR,TX_ADDRESS,TX_ADR_WIDTH);
  126.   NRF_WriteBuf(WRITE_REG + RX_ADDR_P0,RX_ADDRESS,RX_ADR_WIDTH);
  127.   NRF_WriteReg(WRITE_REG + EN_AA,0x01);
  128.   NRF_WriteReg(WRITE_REG + EN_RXADDR,0x01);
  129.   NRF_WriteReg(WRITE_REG + RF_CH,0);
  130.   NRF_WriteReg(WRITE_REG + RX_PW_P0,RX_PLOAD_WIDTH);
  131.   NRF_WriteReg(WRITE_REG + RF_SETUP,0x07);
  132. }
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