FPGA 加三移位法怎么用vhdl语言写?

2019-07-15 20:37发布

FPGA 加三移位法,有人用vhdl 语言写过吗
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tinlyxian
1楼-- · 2019-07-16 00:46
可以参考下
  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;

  4. entity bin8bcd is
  5.     port (
  6.         bin:    in  std_logic_vector (7 downto 0);
  7.         bcd:    out std_logic_vector (11 downto 0)
  8.     );
  9. end entity;

  10. architecture struct of bin8bcd is
  11.     procedure add3 (signal bin: in  std_logic_vector (3 downto 0);
  12.                     signal bcd: out std_logic_vector (3 downto 0)) is
  13.     variable is_gt_4:  std_logic;
  14.     begin
  15.         is_gt_4 := bin(3) or (bin(2) and (bin(1) or bin(0)));

  16.         if is_gt_4 = '1' then
  17.         -- if to_integer(unsigned (bin)) > 4 then
  18.             bcd <= std_logic_vector(unsigned(bin) + "0011");
  19.         else
  20.             bcd <= bin;
  21.         end if;
  22.     end procedure;

  23.     signal U0bin,U1bin,U2bin,U3bin,U4bin,U5bin,U6bin:
  24.                 std_logic_vector (3 downto 0);

  25.     signal U0bcd,U1bcd,U2bcd,U3bcd,U4bcd,U5bcd,U6bcd:
  26.                 std_logic_vector (3 downto 0);      
  27. begin
  28.     U0bin <= '0' & bin (7 downto 5);
  29.     U1bin <= U0bcd(2 downto 0) & bin(4);
  30.     U2bin <= U1bcd(2 downto 0) & bin(3);
  31.     U3bin <= U2bcd(2 downto 0) & bin(2);
  32.     U4bin <= U3bcd(2 downto 0) & bin(1);

  33.     U5bin <= '0' & U0bcd(3) & U1bcd(3) & U2bcd(3);
  34.     U6bin <= U5bcd(2 downto 0) & U3bcd(3);

  35. U0: add3(U0bin,U0bcd);

  36. U1: add3(U1bin,U1bcd);

  37. U2: add3(U2bin,U2bcd);

  38. U3: add3(U3bin,U3bcd);

  39. U4: add3(U4bin,U4bcd);

  40. U5: add3(U5bin,U5bcd);

  41. U6: add3(U6bin,U6bcd);

  42. OUTP:
  43.     bcd <= '0' & '0' & U5bcd(3) & U6bcd & U4bcd & bin(0);

  44. end architecture;

  45. library ieee;
  46. use ieee.std_logic_1164.all;
  47. use ieee.numeric_std.all;

  48. entity bin8bcd_tb is
  49. end entity;

  50. architecture foo of bin8bcd_tb is
  51.     signal bin: std_logic_vector (7 downto 0) := (others => '0');
  52.     -- (initialized to prevent those annoying metavalue reports)

  53.     signal bcd: std_logic_vector (11 downto 0);

  54. begin

  55. DUT:
  56.     entity work.bin8bcd
  57.         port map (
  58.             bin => bin,
  59.             bcd => bcd
  60.         );

  61. STIMULUS:
  62.     process

  63.     begin
  64.         for i in 0 to 255 loop
  65.             bin <= std_logic_vector(to_unsigned(i,8));
  66.             wait for 1 ns;
  67.         end loop;
  68.         wait for 1 ns;
  69.         wait;
  70.     end process;
  71. end architecture;
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