可以参考下

1. library ieee;
   
2. use ieee.std_logic_1164.all;
   
3. use ieee.numeric_std.all;
   
4. 
   
5. entity bin8bcd is
   
6.     port (
   
7.         bin:    in  std_logic_vector (7 downto 0);
   
8.         bcd:    out std_logic_vector (11 downto 0)
   
9.     );
   
10. end entity;
    
11. 
    
12. architecture struct of bin8bcd is
    
13.     procedure add3 (signal bin: in  std_logic_vector (3 downto 0);
    
14.                     signal bcd: out std_logic_vector (3 downto 0)) is
    
15.     variable is_gt_4:  std_logic;
    
16.     begin
    
17.         is_gt_4 := bin(3) or (bin(2) and (bin(1) or bin(0)));
    
18. 
    
19.         if is_gt_4 = '1' then
    
20.         -- if to_integer(unsigned (bin)) > 4 then
    
21.             bcd <= std_logic_vector(unsigned(bin) + "0011");
    
22.         else
    
23.             bcd <= bin;
    
24.         end if;
    
25.     end procedure;
    
26. 
    
27.     signal U0bin,U1bin,U2bin,U3bin,U4bin,U5bin,U6bin:
    
28.                 std_logic_vector (3 downto 0);
    
29. 
    
30.     signal U0bcd,U1bcd,U2bcd,U3bcd,U4bcd,U5bcd,U6bcd:
    
31.                 std_logic_vector (3 downto 0);      
    
32. begin
    
33.     U0bin <= '0' & bin (7 downto 5);
    
34.     U1bin <= U0bcd(2 downto 0) & bin(4);
    
35.     U2bin <= U1bcd(2 downto 0) & bin(3);
    
36.     U3bin <= U2bcd(2 downto 0) & bin(2);
    
37.     U4bin <= U3bcd(2 downto 0) & bin(1);
    
38. 
    
39.     U5bin <= '0' & U0bcd(3) & U1bcd(3) & U2bcd(3);
    
40.     U6bin <= U5bcd(2 downto 0) & U3bcd(3);
    
41. 
    
42. U0: add3(U0bin,U0bcd);
    
43. 
    
44. U1: add3(U1bin,U1bcd);
    
45. 
    
46. U2: add3(U2bin,U2bcd);
    
47. 
    
48. U3: add3(U3bin,U3bcd);
    
49. 
    
50. U4: add3(U4bin,U4bcd);
    
51. 
    
52. U5: add3(U5bin,U5bcd);
    
53. 
    
54. U6: add3(U6bin,U6bcd);
    
55. 
    
56. OUTP:
    
57.     bcd <= '0' & '0' & U5bcd(3) & U6bcd & U4bcd & bin(0);
    
58. 
    
59. end architecture;
    
60. 
    
61. library ieee;
    
62. use ieee.std_logic_1164.all;
    
63. use ieee.numeric_std.all;
    
64. 
    
65. entity bin8bcd_tb is
    
66. end entity;
    
67. 
    
68. architecture foo of bin8bcd_tb is
    
69.     signal bin: std_logic_vector (7 downto 0) := (others => '0');
    
70.     -- (initialized to prevent those annoying metavalue reports)
    
71. 
    
72.     signal bcd: std_logic_vector (11 downto 0);
    
73. 
    
74. begin
    
75. 
    
76. DUT:
    
77.     entity work.bin8bcd
    
78.         port map (
    
79.             bin => bin,
    
80.             bcd => bcd
    
81.         );
    
82. 
    
83. STIMULUS:
    
84.     process
    
85. 
    
86.     begin
    
87.         for i in 0 to 255 loop
    
88.             bin <= std_logic_vector(to_unsigned(i,8));
    
89.             wait for 1 ns;
    
90.         end loop;
    
91.         wait for 1 ns;
    
92.         wait;
    
93.     end process;
    
94. end architecture;

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