verilog模拟spi发数据，数据线比时钟线多一位延迟

2019-07-15 20:44发布

<span style="" >module abc(  clk,
         rst_n,
            spi_clk,
               somi,
         cs,
      simo);


input clk;
input rst_n;
output reg spi_clk;
output  cs;
input somi;
output  reg simo;

//---------------10MHz to 500KHz divided by 20-----------------------

parameter N = 3'd5;
parameter M = 5'd20;
reg [N-1:0]clk_count;

always@(posedge clk or negedge rst_n)
begin
   if(!rst_n)
      begin
         clk_count <= 5'b0;
         spi_clk <= 1'b0;
      end
   else if(clk_count == M/2-1)
      begin
         spi_clk <= ~spi_clk;
         clk_count <= 5'b0;
      end
      else
      begin
                     clk_count <= 5'b0;
         clk_count <= clk_count+1'b1;
      end
end

//---------------------------------------------------------------
// data transfer
reg cs;
reg [7:0]tx;
reg [7:0]txd;

always@ (posedge clk or negedge rst_n)
begin
if(!rst_n)
      begin
                              tx <=8'ha9;
         end
   else
         begin
                              txd <= tx;
         end
end

reg [3:0]ShiftCounter;

// 移位
always@(posedge spi_clk or negedge rst_n)
begin
  if(!rst_n)
   begin
      simo <= 1'bz;
      cs <= 1;
   end
      else  if(ShiftCounter == 4'd8)
            begin
            simo <= 1'bz;
                     cs <= 1;
            end
      else
   begin
         cs <= 0;
   end
end


//上升沿处理// transmit data to mcu
always@(posedge spi_clk or negedge rst_n)
   if(!rst_n)
         begin
         ShiftCounter <= 4'd0;
         simo <= 1'bz;
         end
   else if(~cs)
         begin
               simo <= txd[7-ShiftCounter];
         ShiftCounter <= ShiftCounter + 4'd1;

               if(ShiftCounter == 4'd8)
                        ShiftCounter <= 4'd0;
         end

endmodule

两次片选拉高之间8个时钟，现在是9个，大家看看是什么问题

时序图