FPGA

程序没错误，但quartus软件报错了，但不知到什么原因？

2019-07-15 20:47发布

站内问答 / FPGA
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library ieee;
use ieee.std_logic_1664.all;
use ieee.std_lodic_unsigned.all;
entity cnt10 is
    port (clk,rst,en,load:in std_logic;
        data :in std_logic_vector(3 downto 0);
        DOUT :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        COUT : OUT STD_LOGIC);
end cnt10;
architecture behav of cnt10 is
begin
    process(clk,res,en,load)
        variable q : std_logic_vector(3 downto 0);
    begin
      if rst='0' then q := (others=>'0');
        elsif clk'event and clk='1' then
           if en='1' then
             if (load='0') then q :=data; else
               if q<9 then  q:=q+1;
                 else q := (others=>'0'); end if;
              end if;
            end if;
    end if;
    if q="1001"  then cout<='1'; else  cout<='0';end if;
        dout <= q ;
   end process;
end behav;  
以上程序没问题，但是软件还是报错了。以下时报错内容，请大神们告诉我一下原因，万分感谢
     Error (10481): VHDL Use Clause error at vhdl1.vhd(2): design library "ieee" does not contain primary unit "std_logic_1664"
Error (10800): VHDL error at vhdl1.vhd(2): selected name in use clause is not an expanded name
Error (10481): VHDL Use Clause error at vhdl1.vhd(3): design library "ieee" does not contain primary unit "std_lodic_unsigned"
Error (10800): VHDL error at vhdl1.vhd(3): selected name in use clause is not an expanded name
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 4 errors, 0 warnings
Error: Peak virtual memory: 814 megabytes
Error: Processing ended: Fri Oct 12 11:15:43 2018
Error: Elapsed time: 00:00:16
Error: Total CPU time (on all processors): 00:00:39
Error (293001): Quartus II Full Compilation was unsuccessful. 6 errors, 0 warnings


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2条回答
chumowei
1楼-- · 2019-07-15 22:03
这就怪了 我看你程序开头用了use ieee.std_logic_1664.all;
use ieee.std_lodic_unsigned.all;
lalajie
2楼-- · 2019-07-16 04:02
看了一下果然是打错了吧。。。第一个是1164，第二个是logic不是lodic

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