大神用VHDL写的uart_rx模块，没看明白，请问是在哪里接收的数据？cnt是什么？

FPGA

大神用VHDL写的uart_rx模块，没看明白，请问是在哪里接收的数据？cnt是什么？

2019-07-15 20:52发布

站内问答 / FPGA

2966 6

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_rx is
port(
rst_n :in std_logic:='0';
clk :in std_logic:='0';
data_bits :in std_logic_vector(3 downto 0):="0000";
parity_en :in std_logic_vector(2 downto 0):="000";
rx_bit_in :in std_logic:='1';
rx_dv :out std_logic:='0';
rx_data :out std_logic_vector(7 downto 0):=(others=>'0');
error :out std_logic:='0'
);
end entity;
architecture rtl of uart_rx is
type status_type is ( s_idle,
s_rx_start_bit,
s_rx_data,
s_rx_parity,
s_stop_bit);
signal c_status:status_type:=s_idle;
signal cnt:natural range 0 to 31:=0;
signal rx_data_r:std_logic_vector(7 downto 0):=(others=>'0');
--signal data_bits_r:std_logic_vector(3 downto 0):="0000"; --0101=5 stop bit --0110=6 stop bit --0111=7 stop bit --1000=8 stop bit
--signal parity_en_r:std_logic_vector(2 downto 0):="000"; --0=no parity --1=0 parity --2=1 parity --3=odd parity --4=even parity
signal bit_index:natural range 0 to 8:=0;
signal parity_r:std_logic:='0';
signal rx_bit_r:std_logic:='0';
begin
--数据同步 data synchronization
process(clk)
begin
if rising_edge(clk) then
rx_bit_r<=rx_bit_in;
else
null;
end if;
end process;
process(rst_n,clk)
begin
if rst_n='0' then
c_status<=s_idle;
rx_dv<='0';
rx_data<=(others=>'0');
rx_data_r<=(others=>'0');
error<='0';
bit_index<=0;
cnt<=0;
elsif rising_edge(clk) then
case c_status is
when s_idle => if rx_bit_r='0' then
c_status<=s_rx_start_bit;
else
c_status<=s_idle;
end if;
cnt<=0;
bit_index<=0;
when s_rx_start_bit => if cnt>=6 then
if rx_bit_r='0' then
c_status<=s_rx_data;
else
c_status<=s_idle;
end if;
cnt<=0;
else
c_status<=s_rx_start_bit;
cnt<=cnt+1;
end if;
rx_data_r<=(others=>'0');
rx_dv<='0';
rx_data<=(others=>'0');
error<='0';
when s_rx_data => if cnt>=15 then
cnt<=0;
if bit_index>=(unsigned(data_bits)-1) then
case parity_en is
when "001" => parity_r<='0'; --0 parity
c_status<=s_rx_parity;
when "010" => parity_r<='1'; --1 parity
c_status<=s_rx_parity;
when "011" => parity_r<=(rx_data_r(0) xor rx_data_r(1)) xor
(rx_data_r(2) xor rx_data_r(3)) xor
(rx_data_r(4) xor rx_data_r(5)) xor
(rx_data_r(6) xor rx_data_r(7)) xor '1'; --odd parity (奇校验)
c_status<=s_rx_parity;
when "100" => parity_r<=(rx_data_r(0) xor rx_data_r(1)) xor
(rx_data_r(2) xor rx_data_r(3)) xor
(rx_data_r(4) xor rx_data_r(5)) xor
(rx_data_r(6) xor rx_data_r(7)) ; --even parity (偶校验)
c_status<=s_rx_parity;
when others => c_status<=s_stop_bit;
end case;
bit_index<=0;
else
bit_index<=bit_index+1;
end if;
rx_data_r(bit_index)<=rx_bit_r;
else
cnt<=cnt+1;
end if;
when s_rx_parity => if cnt>=15 then
if rx_bit_r/=parity_r then
error<='1';
else
null;
end if;
c_status<=s_stop_bit;
cnt<=0;
rx_dv<='1';
rx_data<=rx_data_r;
else
cnt<=cnt+1;
c_status<=s_rx_parity;
end if;
when s_stop_bit => if cnt>=15 then
cnt<=0;
c_status<=s_idle;
else
cnt<=cnt+1;
c_status<=s_stop_bit;
end if;
rx_dv<='1';
rx_data<=rx_data_r;
when others => c_status<=s_idle;
rx_dv<='0';
error<='0';
end case;
else
null;
end if;
end process;
end rtl;