请好心人帮我看下错误出现在哪

2019-07-15 20:53发布

顶层文件library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity tongbu isport( load: in std_logic; data: in std_logic_vector(7 downto 0); clock: in std_logic; tongbu_en: in std_logic; delay_en: out std_logic; tongbu_signal: buffer std_logic);end tongbu;architecture tongbu_behave of tongbu iscomponent counterport( clk: in std_logic; enable: in std_logic; load: in std_logic; co: out std_logic; data: in std_logic_vector(7 downto 0); q: buffer std_logic_vector(7 downto 0));end component;signal inter1,inter2: std_logic;signal pr,c,ch,cout: std_logic;signal en_in: std_logic;signal d: std_logic_vector(7 downto 0):="00000100";signal q1,q2: std_logic_vector(7 downto 0):="00000000";signal in_pulse: std_logic;signal comp: std_logic_vector(7 downto 0):="00000001";signal comp_q: std_logic_vector(7 downto 0);signal t_tmp: std_logic:='0';begin pr<=load or c; en_in<=tongbu_en and (not inter1); in_pulse<=ch and (not inter1); process(tongbu_signal,t_tmp) begin if (tongbu_signal'event and tongbu_signal='1')then t_tmp <= not t_tmp; else t_tmp <= t_tmp; end if; end process; delay_en <= t_tmp; process(clock) begin if (clock'event and clock='1')then if (q1="00000000" and q2="00000000")then c <= '1'; else c <= '0'; end if; end if; end process; u1:counter port map (clk=>clock,enable=>en_in,load=>pr,co=>inter1,data=>data,q=>q1); u2:counter port map (clk=>clock,enable=>inter1,load=>pr,co=>inter2,data=>d,q=>q2); process(inter1) variable temp3:integer; begin if (inter1'event and inter1='1')then if (temp3=1) then temp3 := 1; ch <= inter1; else temp3 := temp3+1; end if; end if; end process; process(load,in_pulse,tongbu_en) begin -- if(clock'event and clock='1')then-- load<='1'; if (load ='1')then comp_q <= comp; else if (in_pulse'event and in_pulse='0')then if (tongbu_en='1')then if comp_q="00000000"then comp_q <= "00000000"; cout <= '0'; else comp_q <= comp_q-1; end if; end if; end if; end if;-- end if; end process; tongbu_signal <= in_pulse and cout; end tongbu_behave;底层文件library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;
entity counter is port( clk: in std_logic; enable: in std_logic; load: in std_logic; co: out std_logic; data: in std_logic_vector(7 downto 0); q: buffer std_logic_vector(7 downto 0) );end counter;architecture counter_behave of counter issignal pulse: std_logic;beginprocess(load,data,clk,enable)begin if load='1'then q <= data; elsif clk'event and clk='1'then if enable='1'then q <= q-1; else pulse <= '0'; end if; end if;end process;co <= pulse;end counter_behave;

仿真出来是这样的e[img=0,30]file:///C:UsersAdministratorAppDataRoamingTencentUsers759090627QQWinTempRichOleU0Y[@}AGES)GB8GFEUB)R(L.png[/img]

[img=0,30]file:///C:UsersAdministratorAppDataRoamingTencentUsers759090627QQWinTempRichOleU0Y[@}AGES)GB8GFEUB)R(L.png[/img][img=0,30]file:///C:UsersAdministratorAppDataRoamingTencentUsers759090627QQWinTempRichOleU0Y[@}AGES)GB8GFEUB)R(L.png[/img]

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