这是verilog代码
module adder4 (cout, sum, ina, inb, cin);
input [3:0] ina, inb;
input cin;

output [3:0] sum;
output cout;

assign {cout, sum} = ina+inb+cin;
endmodule



这是仿真
module test_adder4;
reg [3:0] ina, inb;
reg cin;
wire [3:0] sum;
wire cout;

adder4 adder(sum, cout, ina, inb, cin);            //调用测试对象
initial
    begin
        #0  ina = 4'b0001; inb = 4'b1010; cin = 1'b0;
        #5  ina = 4'b0010; inb = 4'b1010; cin = 1'b1;
        #5  ina = 4'b0010; inb = 4'b1110; cin = 1'b0;
        #5  ina = 4'b0011; inb = 4'b1100; cin = 1'b1;
        #5  ina = 4'b0111; inb = 4'b1001; cin = 1'b0;
        #5  ina = 4'b0001; inb = 4'b1100; cin = 1'b1;
        #5  ina = 4'b0011; inb = 4'b1100; cin = 1'b0;
        #5  ina = 4'b0111; inb = 4'b1111; cin = 1'b1;
        #5 $finish;
    end

initial
begin
    $monitor("At time %t, ina(%b) + inb(%b) + cin(%b) = sum(%b) (%2d), cout(%b)",
                $time,ina, inb, cin, sum, sum, cout);
end
endmodule



在vivado2017.3 Run Behavioral Simulation下的运行结果，sum是高阻态，这是为什么呀？