# ** Error: Failure to obtain a Verilog simula
tion license. Unable to checkout any of these license features: alteramtivsim or alteramtivlog.
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./dds_run_msim_rtl_file:///C:/Users/tom/AppData/Local/Temp/%25W@GJ$ACOF(TYDYECOKVDYB.pngverilog.do PAUSED at line 14 请问这个是什么意思 为什么modelsim编译不成功
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