我需要设计一个计数器,时钟变化几十个才计数一次。我先用了一个计数器随时钟计数,然后用组合逻辑判断做加法,modelsim
仿真可以成功但是上板子后无法实现功能,希望大家能帮忙解决一下。
书写的主要代码如下:
always@(count)
begin
if(count==10'd0)
begin
CNP_ON<=1'b0;
CVP_ON<=1'b0;
Inter_Num<=7'd0;
end
else if((count==10'd72)||(count==10'd108)||(count==10'd144)||(count==10'd180)||(count==10'd216))
begin
if(Inter_Num==Max_Inter_Num)
begin
CNP_ON<=1'b0;
Inter_Num<=7'd0;
end
else
begin
Inter_Num<=7'd1;
Inter_Num<=Inter_Num+1'd1;
CNP_ON<=1'b1;
end
end
else if ((count==10'd95)||(count==10'd131)||(count==10'd167)||(count==10'd203)||(count==10'd239))
begin
CNP_ON<=1'b0;
end
else
begin
CNP_ON<=CNP_ON;
Inter_Num<=Inter_Num;
end
end
always@(posedge clk)
begin
if(rst)
begin
count<=10'd0;
end
else if(count<=10'd1022)
begin
count<=count+1'd1;
end
else
begin
count<=count;
end
modelsim仿真结果
FPGA抓取结果
在实际中这样写是无法实现功能的,我该怎么来设计呢,求指教
always@(count)是什么鬼,都改成时钟啊,不要用组合电路,而且组合电路要用“=”不用“<=”,建议你都改成时序电路吧,就是posedge clk这种的,quartus上选无符号数,不要选十进制,那样就有正负了,看着容易误解!
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