求指教的，真心求帮忙指教的。

1楼-- · 2019-07-15 23:40

楼主吧，程序贴出来。大家才会帮你

2楼-- · 2019-07-16 01:38

module sram_test(
clk,rst_n,led,
sram_addr,sram_wr_n,sram_data
);

input clk; // 50MHz
input rst_n; //低电平复位
output led; // LED1

// FPGA与SRAM外部接口
output[14:0] sram_addr; // SRAM地址总线
output sram_wr_n; // SRAM写选通
inout[7:0] sram_data; // SRAM数据总线

//-------------------------------------------------------
reg[25:0] delay; //延时计数器

always @ (posedge clk or negedge rst_n)
if(!rst_n) delay <= 26'd0;
else delay <= delay+1; //不断计数，周期约为1.28s

//-------------------------------------------------------
reg[7:0] wr_data; // SRAM写入数据总线
reg[7:0] rd_data; // SRAM读出数据
reg[14:0] addr_r; // SRAM地址总线
wire sram_wr_req; // SRAM写请求信号
wire sram_rd_req; // SRAM读请求信号
reg led_r; // LED寄存器

assign sram_wr_req = (delay == 26'd9999); //产生写请求信号
assign sram_rd_req = (delay == 26'd19999); //产生读请求信号

always @ (posedge clk or negedge rst_n)
if(!rst_n) wr_data <= 8'd0;
else if(delay == 26'd29999) wr_data <= wr_data+1'b1; //写入数据每1.28s自增1
always @ (posedge clk or negedge rst_n)
if(!rst_n) addr_r <= 15'd0;
else if(delay == 26'd29999) addr_r <= addr_r+1'b1; //写入地址每1.28s自增1

always @ (posedge clk or negedge rst_n)
if(!rst_n) led_r <= 1'b0;
else if(delay == 26'd20099) begin //每1.28s比较一次同一地址写入和读出的数据
if(wr_data == rd_data) led_r <= 1'b1; //写入和读出数据一致，LED点亮
else led_r <= 1'b0; //写入和读出数据不同，LED熄灭
end
assign led = led_r;

//-------------------------------------------------------
`define DELAY_80NS (cnt==3'd7)

reg[2:0] cnt; //延时计数器

always @ (posedge clk or negedge rst_n)
if(!rst_n) cnt <= 3'd0;
else if(cstate == IDLE) cnt <= 3'd0;
else cnt <= cnt+1'b1;

//------------------------------------
parameter IDLE = 4'd0,
WRT0 = 4'd1,
WRT1 = 4'd2,
REA0 = 4'd3,
REA1 = 4'd4;

reg[3:0] cstate,nstate;

always @ (posedge clk or negedge rst_n)
if(!rst_n) cstate <= IDLE;
else cstate <= nstate;

always @ (cstate or sram_wr_req or sram_rd_req or cnt)
case (cstate)
IDLE: if(sram_wr_req) nstate <= WRT0; //进入写状态
   else if(sram_rd_req) nstate <= REA0; //进入读状态
   else nstate <= IDLE;
WRT0: if(`DELAY_80NS) nstate <= WRT1;
   else nstate <= WRT0; //延时等待160ns
WRT1: nstate <= IDLE; //写结束，返回
REA0: if(`DELAY_80NS) nstate <= REA1;
   else nstate <= REA0; //延时等待160ns
REA1: nstate <= IDLE; //读结束，返回
default: nstate <= IDLE;
endcase

//-------------------------------------

assign sram_addr = addr_r; // SRAM地址总线连接

//-------------------------------------
reg sdlink; // SRAM数据总线控制信号

always @ (posedge clk or negedge rst_n)
if(!rst_n) rd_data <= 8'd0;
else if(cstate == REA1) rd_data <= sram_data; //读出数据

always @ (posedge clk or negedge rst_n)
if(!rst_n) sdlink <=1'b0;
else
case (cstate)
IDLE: if(sram_wr_req) sdlink <= 1'b1; //进入连续写状态
   else if(sram_rd_req) sdlink <= 1'b0; //进入单字节读状态
   else sdlink <= 1'b0;
WRT0: sdlink <= 1'b1;
default: sdlink <= 1'b0;
endcase

assign sram_data = sdlink ? wr_data : 8'hzz; // SRAM地址总线连接
assign sram_wr_n = ~sdlink;

endmodule

半飞过

3楼-- · 2019-07-16 03:18

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY write IS
PORT (

   clk       : IN STD_LOGIC;--50MHZ
   rst_n    : IN STD_LOGIC;
   led       : OUT STD_LOGIC;

   sram_addr  : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
   sram_wr_n  : OUT STD_LOGIC;
   sram_data  : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END write;

ARCHITECTURE trans OF write IS

SIGNAL delay    : STD_LOGIC_VECTOR(25 DOWNTO 0);

SIGNAL wr_data    : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL rd_data    : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL addr_r    : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL sram_wr_req : STD_LOGIC;
SIGNAL sram_rd_req : STD_LOGIC;
SIGNAL led_r    : STD_LOGIC;

SIGNAL cnt       : STD_LOGIC_VECTOR(2 DOWNTO 0);
CONSTANT IDLE    : INTEGER := 0;
CONSTANT WRT0    : INTEGER := 1;
CONSTANT WRT1    : INTEGER := 2;
CONSTANT REA0    : INTEGER := 3;
CONSTANT REA1    : INTEGER := 4;

SIGNAL cstate    : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL nstate    : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL sdlink    : STD_LOGIC;

BEGIN
PROCESS (clk, rst_n)
BEGIN
   IF (rst_n = '0') THEN
      delay <= "00000000000000000000000000";
   ELSIF (clk'EVENT AND clk = '1') THEN
      delay <= delay + "00000000000000000000000001";
   END IF;
END PROCESS;

  sram_wr_req<='1'  when(delay="00000000000010011100001111");
  sram_rd_req<='1' when(delay="00000000000100111000011111");

PROCESS (clk, rst_n)
BEGIN
   IF (rst_n = '0') THEN
      wr_data <= "0000000000000000";
   ELSIF (clk'EVENT AND clk = '1') THEN
      IF (delay = "0000000000111010100101111") THEN
         wr_data <= wr_data + "0000000000000001";
      END IF;
   END IF;
END PROCESS;

PROCESS (clk, rst_n)
BEGIN
   IF (rst_n = '0') THEN
      addr_r <= "000000000000000000";
   ELSIF (clk'EVENT AND clk = '1') THEN
      IF (delay = "00000000000111010100101111") THEN
         addr_r <= addr_r + "000000000000000001";
      END IF;
   END IF;
END PROCESS;

PROCESS (clk, rst_n)
BEGIN
   IF (rst_n = '0') THEN
      led_r <= '0';
   ELSIF (clk'EVENT AND clk = '1') THEN
      IF (delay = "00000000000100111010000011") THEN
         IF (wr_data = rd_data) THEN
            led_r <= '1';
         ELSE
            led_r <= '0';
         END IF;
      END IF;
   END IF;
END PROCESS;

led <= led_r;
PROCESS (clk, rst_n)
BEGIN
   IF (rst_n = '0') THEN
      cnt <= "000";
   ELSIF (clk'EVENT AND clk = '1') THEN
      IF (cstate =IDLE) THEN
         cnt<="000";
      ELSE
         cnt <= cnt + "001";--延时计数器

      END IF;
   END IF;
END PROCESS;

PROCESS (clk, rst_n)
BEGIN
   IF (rst_n = '0') THEN
      cstate <="0000";
   ELSIF (clk'EVENT AND clk = '1') THEN
      cstate <= nstate;
   END IF;
END PROCESS;

PROCESS (cstate, sram_wr_req, sram_rd_req, cnt)
BEGIN
   CASE cstate IS
      WHEN "0000" =>IF (sram_wr_req = '1') THEN
            nstate <= "0001";
         ELSIF (sram_rd_req = '1') THEN
            nstate <= "0011";
         ELSE
            nstate <= "0000" ;
         END IF;
      WHEN "0001" =>
         IF (cnt = "111") THEN
            nstate <= "0010";
         ELSE
            nstate <="0001";
         END IF;
      WHEN "0010" =>
         nstate <= "0000";
      WHEN "0011" =>
         IF (cnt = "111") THEN
            nstate <="0100";
         ELSE
            nstate <= "0011";
         END IF;
      WHEN "0100"=>
         nstate <= "0000";
      WHEN OTHERS =>
         nstate <= "0000";
   END CASE;
END PROCESS;

sram_addr <= addr_r;

PROCESS (clk, rst_n)
BEGIN
   IF (rst_n = '0') THEN
      rd_data <= "0000000000000000";
   ELSIF (clk'EVENT AND clk = '1') THEN
      IF (cstate = "0100") THEN
         rd_data <= sram_data;
      END IF;
   END IF;
END PROCESS;

PROCESS (clk, rst_n)
BEGIN
   IF (rst_n = '0') THEN
      sdlink <= '0';
   ELSIF (clk'EVENT AND clk = '1') THEN
      CASE cstate IS
         WHEN "0000"  =>
            IF (sram_wr_req = '1') THEN
               sdlink <= '1';
            ELSIF (sram_rd_req = '1') THEN
               sdlink <= '0';
            ELSE
               sdlink <= '0';
            END IF;
         WHEN "0001" =>
            sdlink <= '1';
         WHEN OTHERS =>
            sdlink <= '0';
      END CASE;
   END IF;
END PROCESS;

--sdlink
sram_data <= wr_data WHEN (sdlink = '1') ELSE --sdlink 1
            "00000000ZZZZZZZZ";
sram_wr_n <= NOT(sdlink);

END trans;
VHDL语言改写的，波形仿真不对，delay总是加到50，在清零了。

半飞过

4楼-- · 2019-07-16 07:31

在搭建sdram核时，新建qsys工程，按照引脚分配表分配的，然后隐藏的引脚我也释放了，但在qsys工程上依旧没有显示出来，Assignment planner 显示引脚已经分配了，然后编译没有报错，继续进行下一步创建nios时，出现No Nios II target connection paths were located. Check connections and that a Nios II .sof is downloaded，我是按照教程步骤走的，只不过板子型号不同，按照这个