library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
en
tity pdiv is
port(
clk : in std_logic;
p : in std_logic_vector(4 downto 0);
k_xor : out std_logic;
k1 : out std_logic;
k2 : out std_logic
);
end pdiv;
architecture rtl of pdiv is
signal m1 : std_logic;
signal m2 : std_logic;
signal c0 : std_logic_vector(4 downto 0);
signal c1 : std_logic_vector(4 downto 0);
signal c2 : std_logic_vector(4 downto 0);
signal c3 : std_logic_vector(4 downto 0);
begin
c0<=p + p;
c3 <=p + 1;
process(clk,c1)
begin
if rising_edge(clk)then
if(c1=c0)then
c1<="00000";
else c1<=c1+1;
end if;
if(c1="00000")then
m1<=not m1;
elsif(c1=c3)then
m1<=not m1;
end if;
end if;
end process;
process(clk,c2)
begin
if rising_edge(clk)then
if(c2=c0)then
c2<="00000";
else c2<=c2+1;
end if;
if(c2="00000")then
m2<=not m2;
elsif(c2=p)then
m2<=not m2;
end if;
end if;
end process;
k1<=m1;
k2<=m2;
k_xor<=m1 xor m2;
end rtl;
一周热门 更多>