module Counter200(clk,rst_n,cnt);
input clk;
input rst_n;
output reg [7:0] cnt;
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
cnt <= 8'b0;
end
else if(cnt == 200) begin
cnt <= 8'd200;
end
else begin
cnt <= cnt + 8'd1;
end
end
endmodule
{var%20f='http://v.t.sina.com.cn/share/share.php?appkey=1515056452',u=z||d.location,p=['&url=',e(u),'&title=',e(t||d.title),'&source=',e(r),'&sourceUrl=',e(l),'&content=',c||'gb2312','&pic=',e(p||'')].join('');function%20a(){if(!window.open([f,p].join(''),'mb',['toolbar=0,status=0,resizable=1,width=440,height=430,left=',(s.width-440)/2,',top=',(s.height-430)/2].join('')))u.href=[f,p].join('');};if(/Firefox/.test(navigator.userAgent))setTimeout(a,0);else%20a();})(screen,document,encodeURIComponent,'','','https://www.xiaopingtou.cn/data/attach/logo/logo.png', '推荐 tmmdh 的问题《求一个verilog的计数器》','https://www.xiaopingtou.net/q-46438.html','页面编码gb2312|utf-8默认gb2312'));){kind=link}
input clk;
input rst_n;
output reg [7:0] cnt;
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
cnt <= 8'b0;
end
else if(cnt == 200) begin
cnt <= 8'd200;
end
else begin
cnt <= cnt + 8'd1;
end
end
endmodule
一周热门 更多>