新手求大神帮忙解释一下下面的程序，另外下面的程序在试验箱上只能点亮一个数码管，怎样修改才能点亮两个
数码管，试验箱芯片是ACEX1K系列，
显示模块
--XSKZ.VHD
LIBRARY IEEE;  
USE IEEE.STD_LOGIC_1164.ALL;  
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENtiTY XSKZ IS  
PORT(EN45,EN25,EN05M,EN05B:IN STD_LOGIC;  
--AIN45M,AIN45B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);  
--AIN25M,AIN25B,AIN05:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTM,DOUTB:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY XSKZ;  
ARCHITECTURE ART OF XSKZ IS
AIN45M,AIN45B: STD_LOGIC_VECTOR(7 DOWNTO 0);
AIN25M,AIN25B,AIN05:IN STD_LOGIC_VECTOR(7 DOWNTO 0);   
BEGIN  
PROCESS(EN45,EN25,EN05M,EN05B)IS
BEGIN  
IF EN45='1'THEN  
DOUTM<=AIN45M(7 DOWNTO 0);DOUTB<=AIN45B(7 DOWNTO 0);
ELSIF EN05M='1'THEN  
DOUTM<=AIN05(7 DOWNTO 0);DOUTB<=AIN05(7 DOWNTO 0);
ELSIF EN25='1'THEN  
DOUTM<=AIN25M(7 DOWNTO 0);DOUTB<=AIN25B(7 DOWNTO 0);
ELSIF EN05B='1'THEN  
DOUTM<=AIN05(7 DOWNTO 0);DOUTB<=AIN05(7 DOWNTO 0);
END IF;  
END PROCESS;  
END ARCHITECTURE ART;
控制模块
LIBRARY IEEE;  
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY JTDKZ IS  
PORT(CLK,SM,SB:IN STD_LOGIC;  
           MR,MY,MG,BR,BY,BG:OUT STD_LOGIC);   
END ENTITY JTDKZ;  
ARCHITECTURE ART OF JTDKZ IS
TYPE STATE_TYPE IS(A,B,C,D);
SIGNAL STATE:STATE_TYPE;
BEGIN  
CNT:PROCESS(CLK)IS  
VARIABLE S:INTEGER RANGE 0 TO 45;
VARIABLE CLR,EN:BIT;
BEGIN  
IF(CLK'EVENT AND CLK='1') THEN
IF CLR='0'THEN
      S:=0;  
ELSIF EN='0'THEN
      S:=S;
ELSE  
      S:=S+1;
END IF;  
CASE STATE IS  
WHEN A=>MR<='0';MY<='0';MG<='1';
BR<='1';BY<='0';BG<='0';
IF(SB AND SM)='1'THEN
IF S=45 THEN  
STATE<=B;CLR:='0';EN:='0';
ELSE  
STATE<=A;CLR:='1';EN:='1';
END IF;  
ELSIF(SB AND (NOT SM))='1'THEN
STATE<=B;CLR:='0';EN:='0';
ELSE  
STATE<=A;CLR:='1';EN:='1';
END IF;  
WHEN B=>MR<='0';MY<='1';MG<='0';
BR<='1';BY<='0';BG<='0';
IF S=5 THEN  
STATE<=C;CLR:='0';EN:='0';
ELSE  
STATE<=B;CLR:='1';EN:='1';
END IF;
WHEN C=>MR<='1';MY<='0';MG<='0';
BR<='0';BY<='0';BG<='1';
IF(SM AND SB)='1'THEN
IF S=25 THEN  
STATE<=D;CLR:='0';EN:='0';
ELSE  
STATE<=C;CLR:='1';EN:='1';
END IF;  
ELSIF SB='0'THEN  
STATE<=D;CLR:='0';EN:='0';
ELSE
STATE<=C;CLR:='1';EN:='1';
END IF;  
WHEN D=>MR<='1';MY<='0';MG<='0';
BR<='0';BY<='1';BG<='0';
IF S=5 THEN  
STATE<=A;CLR:='0';EN:='0';
ELSE  
STATE<=D;CLR:='1';EN:='1';
END IF;
END CASE;
END IF;  
END PROCESS CNT;
END ARCHITECTURE ART;
计时模块
----CNT45S.VHD
LIBRARY IEEE;  
USE IEEE.STD_LOGIC_1164.ALL;  
USE IEEE.STD_LOGIC_UNSIGNED.ALL;  
ENTITY CNT45S IS
PORT  (SB,CLK,EN45:IN STD_LOGIC;  
DOUT45M,DOUT45B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY CNT45S;
ARCHITECTURE ART OF CNT45S IS  
SIGNAL CNT6B:STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN  
PROCESS(SB,CLK,EN45) IS
BEGIN  
IF SB='0' THEN CNT6B<=CNT6B-CNT6B-1;
ELSIF(CLK'EVENT AND CLK='1')THEN
IF EN45='1' THEN CNT6B<=CNT6B+1;  
ELSIF EN45='0' THEN CNT6B<=CNT6B-CNT6B-1;
END IF;
END IF;  
END PROCESS;  
PROCESS(CNT6B)IS
BEGIN  
CASE CNT6B IS  
WHEN"000000"=>DOUT45M<="00111111";DOUT45B<="00111111";
WHEN"000001"=>DOUT45M<="00111111";DOUT45B<="00000110";
WHEN"000010"=>DOUT45M<="00111111";DOUT45B<="01011011";
WHEN"000011"=>DOUT45M<="00111111";DOUT45B<="01001111";
WHEN"000100"=>DOUT45M<="00111111";DOUT45B<="01100110";
WHEN"000101"=>DOUT45M<="00111111";DOUT45B<="01101101";
WHEN"000110"=>DOUT45M<="00111111";DOUT45B<="01111101";
WHEN"000111"=>DOUT45M<="00111111";DOUT45B<="00000111";
WHEN"001000"=>DOUT45M<="00111111";DOUT45B<="01111111";
WHEN"001001"=>DOUT45M<="00111111";DOUT45B<="01101111";
WHEN"001010"=>DOUT45M<="00000110";DOUT45B<="00111111";
WHEN"001011"=>DOUT45M<="00000110";DOUT45B<="00000110";
WHEN"001100"=>DOUT45M<="00000110";DOUT45B<="01011011";
WHEN"001101"=>DOUT45M<="00000110";DOUT45B<="01001111";
WHEN"001110"=>DOUT45M<="00000110";DOUT45B<="01100110";
WHEN"001111"=>DOUT45M<="00000110";DOUT45B<="01101101";
WHEN"010000"=>DOUT45M<="00000110";DOUT45B<="01111101";
WHEN"010001"=>DOUT45M<="00000110";DOUT45B<="00000111";
WHEN"010010"=>DOUT45M<="00000110";DOUT45B<="01111111";
WHEN"010011"=>DOUT45M<="00000110";DOUT45B<="01101111";
WHEN"010100"=>DOUT45M<="01011011";DOUT45B<="00111111";
WHEN"010101"=>DOUT45M<="01011011";DOUT45B<="00000110";
WHEN"010110"=>DOUT45M<="01011011";DOUT45B<="01011011";   
WHEN"010111"=>DOUT45M<="01011011";DOUT45B<="01001111";
WHEN"011000"=>DOUT45M<="01011011";DOUT45B<="01100110";
WHEN"011001"=>DOUT45M<="01011011";DOUT45B<="01101101";
WHEN"011010"=>DOUT45M<="01011011";DOUT45B<="01111101";
WHEN"011011"=>DOUT45M<="01011011";DOUT45B<="00000111";
WHEN"011100"=>DOUT45M<="01011011";DOUT45B<="01111111";
WHEN"011101"=>DOUT45M<="01011011";DOUT45B<="01101111";
WHEN"011110"=>DOUT45M<="01001111";DOUT45B<="00111111";
WHEN"011111"=>DOUT45M<="01001111";DOUT45B<="00000110";
WHEN"100000"=>DOUT45M<="01001111";DOUT45B<="01011011";
WHEN"100001"=>DOUT45M<="01001111";DOUT45B<="01001111";
WHEN"100010"=>DOUT45M<="01001111";DOUT45B<="01100110";
WHEN"100011"=>DOUT45M<="01001111";DOUT45B<="01101101";
WHEN"100100"=>DOUT45M<="01001111";DOUT45B<="01111101";
WHEN"100101"=>DOUT45M<="01001111";DOUT45B<="00000111";
WHEN"100110"=>DOUT45M<="01001111";DOUT45B<="01111111";
WHEN"100111"=>DOUT45M<="01001111";DOUT45B<="01101111";
WHEN"101000"=>DOUT45M<="01100110";DOUT45B<="00111111";
WHEN"101001"=>DOUT45M<="01100110";DOUT45B<="00000110";
WHEN"101010"=>DOUT45M<="01100110";DOUT45B<="01011011";
WHEN"101011"=>DOUT45M<="01100110";DOUT45B<="01001111";
WHEN"101100"=>DOUT45M<="01100110";DOUT45B<="01100110";
WHEN OTHERS=>DOUT45M<="00000000";DOUT45B<="00000000";
END CASE;
END PROCESS;  
END ARCHITECTURE ART;

LIBRARY IEEE;  
USE IEEE.STD_LOGIC_1164.ALL;  
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT25S IS  
PORT(SB,SM,CLK,EN25:IN STD_LOGIC;  
DOUT25M,DOUT25B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY ;  
ARCHITECTURE ART OF CNT25S IS
SIGNAL CNT5B:STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN  
PROCESS (SB,SM,CLK,EN25) IS
BEGIN  
IF SB='0' OR SM='0'THEN
CNT5B<=CNT5B-CNT5B-1;  
ELSIF(CLK'EVENT AND CLK='1')THEN
IF EN25='1'THEN   
CNT5B<=CNT5B+1;
ELSIF EN25='0'THEN  
CNT5B<=CNT5B-CNT5B-1;
END IF;
END IF;  
END PROCESS;  
PROCESS(CNT5B)IS
BEGIN
CASE CNT5B IS  
WHEN
"00000"=>DOUT25M<="00111111";DOUT25B<="00111111";
WHEN
"00001"=>DOUT25M<="00111111";DOUT25B<="00000110";
WHEN
"00010"=>DOUT25M<="00111111";DOUT25B<="01011011";
WHEN
"00011"=>DOUT25M<="00111111";DOUT25B<="01001111";
WHEN
"00100"=>DOUT25M<="00111111";DOUT25B<="01100110";
WHEN
"00101"=>DOUT25M<="00111111";DOUT25B<="01101101";
WHEN
"00110"=>DOUT25M<="00111111";DOUT25B<="01111101";
WHEN
"00111"=>DOUT25M<="00111111";DOUT25B<="00000111";
WHEN
"01000"=>DOUT25M<="00111111";DOUT25B<="01111111";
WHEN
"01001"=>DOUT25M<="00111111";DOUT25B<="01101111";
WHEN
"01010"=>DOUT25M<="00000110";DOUT25B<="00111111";
WHEN
"01011"=>DOUT25M<="00000110";DOUT25B<="00000110";
WHEN
"01100"=>DOUT25M<="00000110";DOUT25B<="01011011";
WHEN
"01101"=>DOUT25M<="00000110";DOUT25B<="01001111";
WHEN
"01110"=>DOUT25M<="00000110";DOUT25B<="01100110";
WHEN
"01111"=>DOUT25M<="00000110";DOUT25B<="01101101";
WHEN
"10000"=>DOUT25M<="00000110";DOUT25B<="01111101";
WHEN
"10001"=>DOUT25M<="00000110";DOUT25B<="00000111";
WHEN
"10010"=>DOUT25M<="00000110";DOUT25B<="01111111";
WHEN
"10011"=>DOUT25M<="00000110";DOUT25B<="01101111";
WHEN
"10100"=>DOUT25M<="01011011";DOUT25B<="00111111";
WHEN
"10101"=>DOUT25M<="01011011";DOUT25B<="00000110";
WHEN
"10110"=>DOUT25M<="01011011";DOUT25B<="01011011";
WHEN
"10111"=>DOUT25M<="01011011";DOUT25B<="01001111";
WHEN
"11000"=>DOUT25M<="01011011";DOUT25B<="01100110";
WHEN
OTHERS=>DOUT25M<="00000000";DOUT25B<="00000000";
END CASE;
END PROCESS;  
END ARCHITECTURE ART;
LIBRARY IEEE;  
USE IEEE.STD_LOGIC_1164.ALL;  
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT05S IS
PORT (CLK,EN05M,EN05B:IN STD_LOGIC;  
DOUT5:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY CNT05S;
ARCHITECTURE ART OF CNT05S IS  
SIGNAL CNT3B:STD_LOGIC_VECTOR(2 DOWNTO
0);
BEGIN  
PROCESS(CLK,EN05M,EN05B) IS
BEGIN  
IF(CLK'EVENT AND CLK='1')THEN  
IF EN05M='1' THEN CNT3B<=CNT3B+1;
ELSIF EN05B='1' THEN CNT3B<=CNT3B+1;  
ELSIF EN05B='0' THEN CNT3B<=CNT3B-CNT3B-1;
END IF;
END IF;  
END PROCESS;  
PROCESS(CNT3B)IS
BEGIN  
CASE CNT3B IS  
WHEN"000"=>DOUT5<="00111111";
WHEN"001"=>DOUT5<="00000110";
WHEN"010"=>DOUT5<="01011011";
WHEN"011"=>DOUT5<="01001111";
WHEN"100"=>DOUT5<="01100110";
WHEN OTHERS=>DOUT5<="00000000";
END CASE;
END PROCESS;  
END ARCHITECTURE ART;