新手，跪求spi串口程序-第2页回答

言尽于此33

1楼-- · 2019-07-17 06:09

紫藤遐想发表于 2016-1-18 21:20
这个网上很多啊，你去找找就可以了。。。。。。

木有呀，大神你有吗。。。。。。。。。。。

190595349@qq.co

2楼-- · 2019-07-17 06:43

精彩回答 2 元偷偷看……

言尽于此33

3楼-- · 2019-07-17 07:56

190595349@qq.co 发表于 2016-1-20 11:01
这个....这个，可以说的具体点吗

基于fpga的spi程序都行，我主要参考一下，请问大神有吗

Heng_Ji

4楼-- · 2019-07-17 10:14

之前我用过一个，还可以，需要吗？

Heng_Ji

5楼-- · 2019-07-17 10:59

module spi_receiver
(
//global clock
input clk,
input rst_n,
//mcu spi interface
input spi_cs, //Chip select enable, default:L
input spi_sck , //Data transfer clock
input spi_mosi, //Master output and slave input
// output spi_miso, //Master input and slave output
//user interface
output reg rxd_flag,
output reg [7:0] rxd_data
);
//-------------------------------------
//mcu data sync to fpga
reg spi_cs_r0, spi_cs_r1;
reg spi_sck_r0, spi_sck_r1; //fsmc default 0; 8080 default 1; spi default 0;
reg spi_mosi_r0, spi_mosi_r1;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
spi_cs_r0 <= 1; spi_cs_r1 <= 1; //chip select enable
spi_sck_r0 <= 0; spi_sck_r1 <= 0; //data transfer clock
spi_mosi_r0 <= 0; spi_mosi_r1 <= 0; //Master output and slave input
end
else
begin
spi_cs_r0 <= spi_cs; spi_cs_r1 <= spi_cs_r0;
spi_sck_r0 <= spi_sck; spi_sck_r1 <= spi_sck_r0;
spi_mosi_r0 <= spi_mosi; spi_mosi_r1 <= spi_mosi_r0;
end
end
wire mcu_cs = spi_cs_r1;
wire mcu_data = spi_mosi_r1;
wire mcu_read_flag = (~spi_sck_r1 & spi_sck_r0) ? 1'b1 : 1'b0; //posedge of sck
wire mcu_read_done = (~spi_cs_r1 & spi_cs_r0) ? 1'b1 : 1'b0; //posedge of cs
//-------------------------------------
//sample signal, receive data
reg [3:0] rxd_cnt;
reg [7:0] rxd_data_r;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
rxd_cnt <= 0;
rxd_data_r <= 0;
end
else if(mcu_cs == 1'b0)
begin
if(mcu_read_flag) //posedge of sck
begin
rxd_data_r[3'd7 - rxd_cnt[2:0]] <= mcu_data;
rxd_cnt <= rxd_cnt + 1'b1; //0-7-8
end
else
begin
rxd_cnt <= rxd_cnt;
rxd_data_r <= rxd_data_r;
end
end
else
begin
rxd_cnt <= 0;
rxd_data_r <= rxd_data_r;
end
end
//-------------------------------------------------
//output spi receive data and receive flag
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
rxd_flag <= 0;
rxd_data <= 0;
end
else if(mcu_read_done)
begin
rxd_flag <= 1'b1;
rxd_data <= rxd_data_r;
end
else
begin
rxd_flag <= 0;
rxd_data <= rxd_data;
end
end
endmodule

复制代码

Heng_Ji

6楼-- · 2019-07-17 12:07

module spi_transfer
(
//global clock
input clk,
input rst_n,
//mcu spi interface
input spi_cs, //Chip select enable, default:L
input spi_sck , //Data transfer clock
// input spi_mosi, //Master output and slave input
output reg spi_miso, //Master input and slave output
//user interface
input txd_en, //Transfer enable
input [7:0] txd_data, //Transfer data
output reg txd_flag //Transfer complete signal
);
//-------------------------------------
//mcu data sync to fpga
reg spi_cs_r0, spi_cs_r1;
reg spi_sck_r0, spi_sck_r1; //fsmc default 0; 8080 default 1; spi default 1;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
spi_cs_r0 <= 1; spi_cs_r1 <= 1; //chip select enable
spi_sck_r0 <= 0; spi_sck_r1 <= 0; //data transfer clock
end
else
begin
spi_cs_r0 <= spi_cs; spi_cs_r1 <= spi_cs_r0;
spi_sck_r0 <= spi_sck; spi_sck_r1 <= spi_sck_r0;
end
end
wire mcu_cs = spi_cs_r1;
wire mcu_write_flag = (spi_sck_r1 & ~spi_sck_r0) ? 1'b1 : 1'b0; //nededge of sck
wire mcu_write_done = (~spi_cs_r1 & spi_cs_r0) ? 1'b1 : 1'b0; //posedge of cs
//-------------------------------------
//shift signal, transfer data
localparam SPI_MISO_DEFAULT = 1'b1;
localparam T_IDLE = 1'b0; //test the flag to transfer data
localparam T_SEND = 1'b1; //spi transfer data
reg [1:0] txd_state;
reg [3:0] txd_cnt;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
spi_miso <= SPI_MISO_DEFAULT;
txd_cnt <= 0;
txd_state <= 0;
end
else
begin
case(txd_state)
T_IDLE: //test the flag to transfer data
begin
spi_miso <= SPI_MISO_DEFAULT;
txd_cnt <= 0;
if(txd_en)
txd_state <= T_SEND;
else
txd_state <= T_IDLE;
end
T_SEND: //spi transfer data
begin
if(mcu_write_done == 1'b1)
txd_state <= T_IDLE;
else
txd_state <= T_SEND;
if(mcu_cs == 1'b0)
begin
if(mcu_write_flag) //spi sck negedge
begin
spi_miso <= txd_data[3'd7 - txd_cnt[2:0]];
txd_cnt <= txd_cnt + 1'b1;
end
else
begin
spi_miso <= spi_miso;
txd_cnt <= txd_cnt;
end
end
else
begin
spi_miso <= SPI_MISO_DEFAULT;
txd_cnt <= 0;
end
end
endcase
end
end
//-------------------------------------------------
//output spi transfer flag
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
txd_flag <= 0;
else
txd_flag <= mcu_write_done;
end
endmodule

复制代码

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