module wave_gen(address,inclk,select,freq);
output[8:0] address;
input inclk;
input[1:0] select;
input[3:0] freq;
reg[7:0] Qout;
reg[8:0] adderss;
reg[7:0] k,m;
wire [1:0] select;
parameter sina_wave=2'b00,swat_wave=2'b01,
squr_wave=2'b10,trig_wave=2'b11;
always @(posedge inclk)
begin
case(select)
sina_wave:begin
if(select==2'b01) address<=128;
if(select==2'b10) address<=256;
if(select==2'b11) address<=384;
if(freq==0||freq==1)
begin
if(address>=127) adderss<=0;
else adderss<=address+1;
end
else
begin
k<=127/freq;
m<=freq*k;
if(address>=m)
adderss<=0;
else
adderss<=address+freq;
end
end
swat_wave:begin
if(select==2'b00) address<=0;
if(select==2'b10) address<=256;
if(select==2'b11) address<=384;
if(address < 128) adderss<=128;
else
begin
if(freq==0||freq==1)
begin
if(address>=255) adderss<=128;
else adderss<=address+1;
end
else
begin
k<=127/freq;
m<=freq*k;
if(address>=(m+128))
adderss<=9'd128;
else
adderss<=address+freq;
end
end
end
squr_wave:begin
if(select==2'b00) address<=0;
if(select==2'b01) address<=128;
if(select==2'b11) address<=384;
if(address<256) address<=256;
else
begin
if(freq==0||freq==1)
begin
if(address>=383) adderss<=256;
else adderss<=address+1;
end
else
begin
k<=127/freq;
m<=freq*k;
if(address>=(m+256))
adderss<=256;
else
adderss<=address+freq;
end
end
end
trig_wave:begin
if(select==2'b00) address<=0;
if(select==2'b01) address<=128;
if(select==2'b10) address<=256;
if(address<=384) address<=384;
else
begin
if(freq==0||freq==1)
begin
if(address>=511) adderss<=384;
else adderss<=address+1;
end
else
begin
k<=127/freq;
m<=freq*k;
if(address>=(m+384))
adderss<=384;
else
adderss<=address+freq;
end
end
end
endcase
end
endmodule
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我这里的adderss的值不是0-511个值吗,它作为一个地址,里面存储的是四个波形的值,0-127是一个周期正弦的值,128-255是一个周期锯齿波的值,256-383是一个周期方波的值,384-511是一个周期三角波的值,至于你说的if(select==00)的那些语句,可以不要
是可以这样来产生波形的,我之前也做过,通过数组存储波形数据,然后将数据送至DA,转换出模拟信号,通过滤波输出波形
可是用verilog,怎么表示,我就不会用了。刚开始学,有些语句的用法还不是太了解
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