module Column_scan_seg(
input clk,
input rst_n,
output [1:0] Column_scan
);
reg [18:0] counter1;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
counter1<=19'd0;
else if(counter1==499_999)
counter1<=19'd0;
else
counter1<=counter1+1'b1;
end
reg[1:0] t;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
t<=2'd0;
else if(t==2'd2)
t<=2'd0;
else
t<=t+1'b1;
end
reg [1:0] Column_scan_0;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
Column_scan_0<=2'b10;
else if(counter1==4999_999)
case(t)
2 'd0: Column_scan_0<=2'b10;
2 'd1: Column_scan_0<=2'b01;
endcase
end
assign Column_scan=Column_scan_0;
endmodule
-
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