为什么我每次运行testbench文件以后,除了死机还是死机呢?
又或者社么都没有
这是top文件:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
EN
tiTY CNT10 IS
PORT(CLK,RST,EN,LOAD:IN STD_LOGIC;
DATA:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT:OUT STD_LOGIC);
END CNT10;
ARCHITECTURE BEHAV OF CNT10 IS
BEGIN
PROCESS(CLK,RST,EN,LOAD)
VARIABLE Q:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF RST='0' THEN Q:=(OTHERS=>'0');
ELSIF CLK'EVENT AND CLK='1' THEN
IF EN='1' THEN
IF(LOAD='0') THEN Q:=DATA;ELSE
IF Q<9 THEN Q:=Q+1;
ELSE Q:=(OTHERS=>'0');
END IF;
END IF;
END IF;
END IF;
IF Q="1001" THEN COUT<='1';
ELSE COUT<='0'; END IF;
DOUT<=Q;
END PROCESS;
END BEHAV;
下面是test文件
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY CNT10_vhd_tst IS
END CNT10_vhd_tst;
ARCHITECTURE CNT10_arch OF CNT10_vhd_tst IS
-- constants
-- signals
SIGNAL CLK : STD_LOGIC;
SIGNAL COUT : STD_LOGIC;
SIGNAL DATA : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL DOUT : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL EN : STD_LOGIC;
SIGNAL LOAD : STD_LOGIC;
SIGNAL RST : STD_LOGIC;
SIGNAL CLK_P:TIME:=30 NS;
COMPONENT CNT10
PORT (
CLK : IN STD_LOGIC;
COUT : OUT STD_LOGIC;
DATA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
EN : IN STD_LOGIC;
LOAD : IN STD_LOGIC;
RST : IN STD_LOGIC
);
END COMPONENT;
BEGIN
i1 : CNT10
PORT MAP (
-- list connections between master ports and signals
CLK => CLK,
COUT => COUT,
DATA => DATA,
DOUT => DOUT,
EN => EN,
LOAD => LOAD,
RST => RST
);
init : PROCESS
-- variable declarations
BEGIN
-- code that executes only once
CLK<='0'; WAIT FOR CLK_P;
CLK<='1'; WAIT FOR CLK_P;
END PROCESS init;
always : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations
BEGIN
-- code executes for every event on sensitivity list
RST<='1','0' AFTER 110 NS,'1' AFTER 114 NS;
EN<='0','1' AFTER 40 NS;
LOAD<='1','0' AFTER 910 NS,'1' AFTER 940 NS;
DATA<="0100","0110" AFTER 400 NS,
"0111" AFTER 700 NS,"0100" AFTER 1000 NS;
END PROCESS always;
END CNT10_arch;
请帮忙看看,谢谢,不知道是什么问题,或者是操作上的问题
谢谢先,大神发现我那个.vht里面搞错了,进程没有敏感信号,可以把它删除
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