always @(posedge clk_ref or negedge rst_n)
begin
if(!rst_n)
begin
sdram_wr_req_t=1'b0;
sdram_wraddr_t=22'b0;
sdram_din_t=16'b0;
sdram_rd_req_t=1'b0;
sdram_rdaddr_t=22'b0;
start =1'b0;
start_step=4'b0;
step_test=1'b0;
end
else
begin
if(ram_init_ok && !start)
begin
case (start_step)
4'd0:
begin
sdram_wr_req_t=1'b1;
sdram_wraddr_t=22'h10;
sdram_din_t=16'h0000;
start_step=start_step+1'b1;
end
4'd1:
begin
if(write_done)begin
sdram_wr_req_t=1'b0;
start_step=start_step+1'b1;
// if(TEST_DATA_OUT==16'h00F0)step_test=1'b1;
end
end
4'd2:
begin
sdram_wr_req_t=1'b1;
sdram_wraddr_t=22'h20;
sdram_din_t=16'h0000;
start_step=start_step+1'b1;
end
4'd3:
begin
if(write_done)begin
sdram_wr_req_t=1'b0;
start_step=start_step+1'b1;
end
end
4'd4:
begin
sdram_wr_req_t=1'b1;
sdram_wraddr_t=22'h30;
sdram_din_t=16'h00FE;
start_step=start_step+1'b1;
end
4'd5:
begin
if(write_done)begin
sdram_wr_req_t=1'b0;
start_step=start_step+1'b1;
end
end
4'd6:
begin
sdram_rdaddr_t=22'h10;
sdram_wraddr_t=22'h00;
start_step=start_step+1'b1;
end
4'd7:
begin
sdram_rd_req_t=1'b1;
start_step=start_step+1'b1;
end
4'd8:
begin
if(read_done)begin
color1=sdram_dout[7:0];
sdram_rd_req_t=0;
start_step=start_step+1'b1;
step_test=(color1==8'hfe)?1'b1:1'b0;
end
end
4'd9:
begin
sdram_rd_req_t=1'b1;
sdram_rdaddr_t=22'h20;
start_step=start_step+1'b1;
end
4'd10:
if(read_done)begin
color2=sdram_dout[7:0];
sdram_rd_req_t=0;
start_step=start_step+1'b1;
// step_test=(sdram_dout==16'h0080)?1'b1:1'b0;
end
4'd11:
begin
sdram_rd_req_t=1'b1;
sdram_rdaddr_t=22'h30;
start_step=start_step+1'b1;
end
4'd12:
begin
if(read_done)begin
color3=sdram_dout[7:0];
sdram_rd_req_t=0;
start_step=start_step+1'b1;
// if(sdram_dout[7:0]==8'h70)step_test=1'b1;
start=1'b1;
end
end
default:
start_step=start_step;
endcase
end
end
end
这里是测试的代码
always @(posedge clk_ref or negedge rst_n)
begin
if(!rst_n)
begin
sdram_wr_req_t=1'b0;
sdram_wraddr_t=22'b0;
sdram_din_t=16'b0;
sdram_rd_req_t=1'b0;
sdram_rdaddr_t=22'b0;
start =1'b0;
start_step=4'b0;
step_test=1'b0;
end
else
begin
if(ram_init_ok && !start)
begin
case (start_step)
4'd0:
begin
sdram_wr_req_t=1'b1;
sdram_wraddr_t=22'h10;
sdram_din_t=16'h0000;
start_step=start_step+1'b1;
end
4'd1:
begin
if(write_done)begin
sdram_wr_req_t=1'b0;
start_step=start_step+1'b1;
// if(TEST_DATA_OUT==16'h00F0)step_test=1'b1;
end
end
4'd2:
begin
sdram_wr_req_t=1'b1;
sdram_wraddr_t=22'h20;
sdram_din_t=16'h0000;
start_step=start_step+1'b1;
end
4'd3:
begin
if(write_done)begin
sdram_wr_req_t=1'b0;
start_step=start_step+1'b1;
end
end
4'd4:
begin
sdram_wr_req_t=1'b1;
sdram_wraddr_t=22'h30;
sdram_din_t=16'h00FE;
start_step=start_step+1'b1;
end
4'd5:
begin
if(write_done)begin
sdram_wr_req_t=1'b0;
start_step=start_step+1'b1;
end
end
4'd6:
begin
sdram_rdaddr_t=22'h10;
sdram_wraddr_t=22'h00;
start_step=start_step+1'b1;
end
4'd7:
begin
sdram_rd_req_t=1'b1;
start_step=start_step+1'b1;
end
4'd8:
begin
if(read_done)begin
color1=sdram_dout[7:0];
sdram_rd_req_t=0;
start_step=start_step+1'b1;
step_test=(color1==8'hfe)?1'b1:1'b0;
end
end
4'd9:
begin
sdram_rd_req_t=1'b1;
sdram_rdaddr_t=22'h20;
start_step=start_step+1'b1;
end
4'd10:
if(read_done)begin
color2=sdram_dout[7:0];
sdram_rd_req_t=0;
start_step=start_step+1'b1;
// step_test=(sdram_dout==16'h0080)?1'b1:1'b0;
end
4'd11:
begin
sdram_rd_req_t=1'b1;
sdram_rdaddr_t=22'h30;
start_step=start_step+1'b1;
end
4'd12:
begin
if(read_done)begin
color3=sdram_dout[7:0];
sdram_rd_req_t=0;
start_step=start_step+1'b1;
// if(sdram_dout[7:0]==8'h70)step_test=1'b1;
start=1'b1;
end
end
default:
start_step=start_step;
endcase
end
end
end
就是在地址00,01,02写入数据,再读出来......现在问题是,不管读取什么出来的都是写入02的数据,搞得我都不知道是写入还是读取错误,在每个动作前加入延时也是一样的效果,希望有好心人能够参谋一下
有人吗.....真的需要帮忙啊....
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