FPGA

求救大神，学渣用VHDL编了个与非门，出现简单错误怎么解决

2019-07-16 00:12发布

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本帖最后由 xiaohuihui1989 于 2015-1-17 16:15 编辑

2输入与非门
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENtiTY AND IS
PORT (A,B:IN STD_LOGIC;
Y:OUT STD_LOGIC)
END ENTITY AND;
ARCHITECTURE AND2 OF AND IS
BEGIN
T1:PROCESS(A,B)IS
VARIABLE COMB:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
COMB:=A&B;
CASE COMB IS
WHEN "00"=>Y<='1';
WHEN "01"=>Y<='1';
WHEN "10"=>Y<='1';
WHEN "11"=>Y<='0';
WHEN OTHERS=>Y<='X';
END CASE;
END PROCESS T1;
END ARCHITECTURE AND2;
错误提示为：
Error (10500): VHDL syntax error at AND.vhd(3) near text "AND";  expecting an identifier
Error (10500): VHDL syntax error at AND.vhd(7) near text "AND";  expecting an identifier
求解答

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5条回答
xiaohuihui1989
1楼-- · 2019-07-16 00:45
错误提示为：Error (10500): VHDL syntax error at AND.vhd(3) near text "AND";  expecting an identifier
Error (10500): VHDL syntax error at AND.vhd(7) near text "AND";  expecting an identifier
Jack315
2楼-- · 2019-07-16 05:23
本帖最后由 Jack315 于 2015-1-17 18:52 编辑

LZ 试试这个：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY myAND IS
PORT (A,B:IN STD_LOGIC;
Y:OUT STD_LOGIC) ;
END ENTITY myAND;

ARCHITECTURE AND2 OF myAND IS
BEGIN
T1:PROCESS(A,B)IS
VARIABLE COMB:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
COMB:=A&B;
CASE COMB IS
WHEN "00"=>Y<='1';
WHEN "01"=>Y<='1';
WHEN "10"=>Y<='1';
WHEN "11"=>Y<='0';
WHEN OTHERS=>Y<='X';
END CASE;
END PROCESS T1;
END ARCHITECTURE AND2;

222lyy
3楼-- · 2019-07-16 06:33
AND不能做实体名
haizei51@2980
4楼-- · 2019-07-16 07:04
 精彩回答 2  元偷偷看……
vayneISme
5楼-- · 2019-07-16 11:34
哈，不知道为什么看到你的问题觉得好歹我还是学会了点东西。。。。

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