LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
EN
tiTY EVEN_DIVIDER IS
GENERIC(N:INTEGER :=8);
PORT(
CLKIN: IN STD_LOGIC;
CLKOUT:OUT STD_LOGIC;
CNT:OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END EVEN_DIVIDER;
ARCHITECTURE RTL OF EVEN_DIVIDER IS
SIGNAL COUNT:INTEGER;
BEGIN
该程序实现8分频,送入输入时钟,输出时钟恒为’1‘,请问为何
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY EVEN_DIVIDER IS
GENERIC(N:INTEGER :=8);
PORT(
CLKIN: IN STD_LOGIC;
CLKOUT:OUT STD_LOGIC;
CNT:OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END EVEN_DIVIDER;
ARCHITECTURE RTL OF EVEN_DIVIDER IS
SIGNAL COUNT:INTEGER;
BEGIN
PROCESS (CLKIN)
BEGIN
IF CLKIN'EVENT AND CLKIN='1' THEN
IF COUNT=N-1 THEN
COUNT<=0;
ELSE
COUNT<=COUNT+1;
IF COUNT<INTEGER(N/2) THEN
CLKOUT<='1';
ELSE
CLKOUT<='0';
END IF;
END IF;
END IF;
END PROCESS;
CNT<=CONV_STD_LOGIC_VECTOR(COUNT,3);
END RTL;
上面程序粘掉了
已找到原因,未赋初值
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